公开(公告)号：US11239343B2

公开(公告)日：2022-02-01

申请号：US16797097

申请日：2020-02-21

Applicant: International Business Machines Corporation

Inventor： Chun-Chen Yeh ,  Alexander Reznicek ,  Veeraraghavan Basker ,  Junli Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/223

Abstract: A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness.

公开(公告)号：US20210249506A1

公开(公告)日：2021-08-12

申请号：US16785899

申请日：2020-02-10

Applicant: International Business Machines Corporation

Inventor： Chun-Chen Yeh ,  Veeraraghavan Basker ,  Alexander Reznicek ,  Junli Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a nanosheet field effect transistor (FET) device. The fabrication operations include forming a nanosheet stack over a portion of a substrate. A first source or drain (S/D) trench is formed adjacent to a first end of the nanosheet stack. A second S/D trench is formed adjacent to a second end of the nanosheet stack. A region of the substrate is removed to form a bottom dielectric isolation (BDI) cavity in the substrate, wherein the BDI cavity is positioned beneath at least the nanosheet stack, the first S/D trench, and the second S/D trench. The BDI cavity is filled with a dielectric material, thereby forming a BDI region positioned beneath at least the nanosheet stack, the first S/D trench, and the second S/D trench.

公开(公告)号：US10998234B2

公开(公告)日：2021-05-04

申请号：US16411350

申请日：2019-05-14

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Veeraraghavan Basker ,  Nicolas Loubet ,  Balasubramanian Pranatharthiharan

IPC: H01L21/8234 ,  H01L29/06 ,  H01L21/84 ,  H01L21/02 ,  H01L29/40 ,  H01L29/08 ,  H01L21/762 ,  H01L29/66 ,  H01L27/12 ,  H01L21/3065 ,  H01L29/417 ,  H01L29/78 ,  H01L27/088 ,  H01L27/108 ,  H01L21/311

Abstract: Embodiments of the present invention are directed to a method that prevents punch-through of a bottom isolation layer and improves the quality of the source/drain epitaxial growth in a nanosheet semiconductor structure. In a non-limiting embodiment of the invention, a bottom isolation structure is formed over a substrate. The bottom isolation structure includes a tri-layer stack in a first region of the substrate and a bi-layer stack in a second region of the substrate. A nanosheet stack is formed over the bottom isolation structure in the first region of the substrate. A gate is formed over a channel region of the nanosheet stack.

公开(公告)号：US20200335392A1

公开(公告)日：2020-10-22

申请号：US16387687

申请日：2019-04-18

Applicant: International Business Machines Corporation

Inventor： Adra Carr ,  Vimal Kamineni ,  Ruilong Xie ,  Andrew Greene ,  Nigel Cave ,  Veeraraghavan Basker

IPC: H01L21/768

Abstract: Embodiments of the present invention are directed to reducing the effective capacitance between active devices at the contact level. In a non-limiting embodiment of the invention, an interlayer dielectric is replaced with a low-k material without damaging a self-aligned contact (SAC) cap. A gate can be formed over a channel region of a fin. The gate can include a gate spacer and a SAC cap. Source and drain regions can be formed adjacent to the channel region. A contact is formed on the SAC cap and on surfaces of the source and drain regions. A first dielectric layer can be recessed to expose a sidewall of the contact and a sidewall of the gate spacer. A second dielectric layer can be formed on the recessed surface of the first dielectric layer. The second dielectric layer can include a dielectric material having a dielectric constant less than the first dielectric layer.

公开(公告)号：US20170076993A1

公开(公告)日：2017-03-16

申请号：US15341663

申请日：2016-11-02

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan Basker ,  Kangguo Cheng ,  Theodorus Standaert ,  Junli Wang

IPC: H01L21/8238 ,  H01L29/10 ,  H01L21/308 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31051 ,  H01L21/31056 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/66803

Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.

Abstract translation: 一种技术涉及形成自对准场效应晶体管。 一种起动穿孔止动器，包括一个其上形成有多个翅片的基片，一个n型场效应晶体管（NFET）区，一个p型场效应晶体管（PFET）区，以及一个具有边界缺陷的中心区 首先提供NFET区域和PFET区域的界面。 然后对场效应晶体管进行掩模以掩蔽NFET区域和PFET区域，使得中心区域被暴露。 然后通过蚀刻中心区域形成中心边界区域以去除边界缺陷。

公开(公告)号：US20160372383A1

公开(公告)日：2016-12-22

申请号：US14741418

申请日：2015-06-16

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan Basker ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/84 ,  H01L29/45 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/265

CPC classification number: H01L21/845 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/456

Abstract: A method of forming field effect transistors (FETs), and forming integrated circuit (IC) chip including the FETs. Gates are formed on said semiconductor fins to define multi fin field effect transistors (FinFETs). Dielectric sidewalls on fins protect the sidewalls while the surface is damaged intentionally, e.g., with an implant that leaves source/drain junctions undisturbed. After removing the dielectric sidewalls semiconductor material is grown epitaxially on the sidewalls with the damage retarding growth on the surface. The epi-growth bridges between fins in the same FET. After the damage is repaired, chip processing continues normally.

Abstract translation: 一种形成场效应晶体管（FET）的方法，以及形成包括FET的集成电路（IC）芯片。 在所述半导体鳍片上形成栅极以限定多鳍场效应晶体管（FinFET）。 翅片上的电介质侧壁保护侧壁，同时有意地损坏表面，例如使植入物不受干扰地离开源极/排水结。 在去除电介质侧壁之后，半导体材料在侧壁上外延生长，并且表面上具有损伤延迟生长。 同一FET中翅片之间的外延生长桥梁。 修复损坏后，芯片处理继续正常。

公开(公告)号：US09373618B1

公开(公告)日：2016-06-21

申请号：US14845442

申请日：2015-09-04

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan Basker ,  Kangguo Cheng ,  Theodorus Standaert ,  Junli Wang

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L49/02 ,  H01L21/8239 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823431 ,  H01L21/8239 ,  H01L27/10826 ,  H01L27/10879 ,  H01L28/60 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/945

Abstract: A technique relates to forming a semiconductor device. A field-effect transistor structure having a substrate, a fin structure patterned in the substrate, a gate stack structure, and an insulator layer is first provided. A non-capacitor region and a capacitor region are then formed on the field-effect transistor structure by masking portions of the field-effect transistor structure with a mask such that a non-capacitor region is masked and a capacitor region is exposed, and etching the insulator layer to further recess the fin structure and gate stack structure within the capacitor region such that a revealed height of the fins within the capacitor region is increased relative to the revealed height of the fins in the non-capacitor region. A high-k layer can be deposited over the recessed fins and gate stack structures and a gate metal can fill the recessed portions therein.

Abstract translation: 技术涉及形成半导体器件。 首先提供具有衬底的场效应晶体管结构，在衬底中图案化的鳍结构，栅堆叠结构和绝缘体层。 然后在场效应晶体管结构上形成非电容器区域和电容器区域，通过用掩模掩蔽场效应晶体管结构的部分，使得非电容器区域被掩蔽并且电容器区域被暴露，并且蚀刻 所述绝缘体层进一步使所述电容器区域内的所述鳍结构和栅极叠层结构凹陷，使得所述电容器区域内的所述散热片的显露高度相对于所述非电容器区域中的散热片的显露高度增加。 高k层可以沉积在凹陷的翅片和栅极堆叠结构上，并且栅极金属可以填充其中的凹陷部分。