公开(公告)号：US20200013891A1

公开(公告)日：2020-01-09

申请号：US16575899

申请日：2019-09-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xuefeng Liu ,  Junli Wang ,  Brent A. Anderson ,  Terence B. Hook ,  Gauri Karve

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/417

Abstract: A semiconductor device includes a substrate having an input/output (IO) field-effect transistor (FET) device area, and an IO FET device formed in the IO FET device area. The IO FET device includes at least two fin structures separated by a distance associated with a length of a channel connecting the at least two fin structures. The length of the channel is determined based on at least one voltage for implementing the IO FET device.

公开(公告)号：US20190341490A1

公开(公告)日：2019-11-07

申请号：US16516477

申请日：2019-07-19

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/78 ,  H03K17/687 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

公开(公告)号：US10424663B2

公开(公告)日：2019-09-24

申请号：US15813523

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H03K17/687 ,  H01L29/786 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

公开(公告)号：US10361127B1

公开(公告)日：2019-07-23

申请号：US15856533

申请日：2017-12-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gauri Karve ,  Fee Li Lie ,  Indira Seshadri ,  Mona Ebrish ,  Leigh Anne H. Clevenger ,  Ekmini A. De Silva ,  Nicole A. Saulnier

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/265 ,  H01L27/088 ,  H01L27/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L21/308 ,  H01L21/3065

Abstract: A method for forming a device with multiple gate lengths includes forming a gate stack on vertical fins. A cutting mask formed on the gate stack is etched to include two or more different heights. Gate structures with two or more gate lengths are etched by employing the two or more different heights in the cutting mask as an etch mask. The cutting mask is removed. A top source/drain regions is formed on top of the vertical fins.

公开(公告)号：US20190189503A1

公开(公告)日：2019-06-20

申请号：US15847005

申请日：2017-12-19

Applicant: International Business Machines Corporation

Inventor： Isabel Cristina Chu ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Ekmini Anuja De Silva ,  Gauri Karve ,  Fee Li Lie ,  Nicole Adelle Saulnier ,  Indira Seshadri ,  Hosadurga Shobha

IPC: H01L21/768 ,  H01L21/66 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76837 ,  H01L21/76819 ,  H01L21/76877 ,  H01L22/14 ,  H01L23/5226 ,  H01L23/53228

Abstract: Apparatus and methods for dielectric gap fill evaluations are provided. In one example, a method can comprise providing a gap fill substrate over one or more interlayer dielectric trenches of a dielectric layer and over a first material located in the one or more interlayer dielectric trenches. The method can also comprise depositing a gap fill candidate material within one or more gap fill substrate trenches of the gap fill substrate. Furthermore, the method can comprise etching the gap fill candidate material until a void within the first material is identified. Additionally, the method can comprise filling the one or more gap fill substrate trenches with a second material to form one or more contacts with the first material to measure a leakage current of one or more pitches.

公开(公告)号：US20190006506A1

公开(公告)日：2019-01-03

申请号：US15639721

申请日：2017-06-30

Applicant: International Business Machines Corporation

Inventor： Andrew M. Greene ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Eric R. Miller ,  Pietro Montanini

IPC: H01L29/78 ,  H01L29/66

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).

公开(公告)号：US20180342614A1

公开(公告)日：2018-11-29

申请号：US15602884

申请日：2017-05-23

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H03K17/687 ,  H01L29/06

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

公开(公告)号：US10121853B2

公开(公告)日：2018-11-06

申请号：US15794636

申请日：2017-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Derrick Liu ,  Soon-Cheon Seo ,  Stuart A. Sieg

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

公开(公告)号：US10032680B2

公开(公告)日：2018-07-24

申请号：US14984215

申请日：2015-12-30

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

公开(公告)号：US20180097002A1

公开(公告)日：2018-04-05

申请号：US15593872

申请日：2017-05-12

Applicant: International Business Machines Corporation

Inventor： Isabel C. Chu ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Mona A. Ebrish ,  Gauri Karve ,  Fee Li Lie ,  Deepika Priyadarshini ,  Nicole A. Saulnier ,  Indira P. Seshadri

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3081 ,  H01L21/31051 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/167

Abstract: A method for forming a semiconductor device includes blocking a first region of a wafer and forming a plurality of fins in a second region of the wafer. A protective conformal mask layer is deposited over the plurality of fins in the second region, the second region is blocked, and a plurality of fins are formed in the first region of the wafer using a variety of wet and/or dry etching procedures. The protective conformal mask layer protects the plurality of fins in the second region from the variety of wet and/or dry etching procedures that are used to form the plurality of fins in the first region.