公开(公告)号：US20150260792A1

公开(公告)日：2015-09-17

申请号：US14205910

申请日：2014-03-12

Applicant: International Business Machines Corporation

Inventor： Garrett M. Drapala ,  Gary E. Strait

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G11C29/04 ,  G06F11/273 ,  G11C29/12 ,  G11C29/40 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52

Abstract: Embodiments relate to matrix and compression-based error detection. An aspect includes summing, by each of a first plurality of summing modules of a first compressor, a respective row of a matrix, the matrix comprising a plurality of rows and a plurality of columns of output bits of a circuit under test wherein each output bit of the circuit under test comprises an element of the matrix, and is a member of a row of a column that is orthogonal to the row. Another aspect includes summing, by each of a second plurality of summing modules of a second compressor, a respective column of output bits of the matrix. Yet another aspect includes determining a presence of an error in the circuit under test based at least one of an output of the first compressor and an output of the second compressor.

Abstract translation: 实施例涉及基于矩阵和基于压缩的错误检测。 一个方面包括由第一压缩器的第一多个求和模块中的每一个相加矩阵的相应行，所述矩阵包括被测电路的多行和多列输出位，其中每个输出位 被测电路包括矩阵的元素，并且是与行正交的列的行的成员。 另一方面包括由第二压缩器的第二多个求和模块中的每一个相加矩阵的相应输出位列。 另一方面包括基于第一压缩机的输出和第二压缩机的输出中的至少一个来确定被测电路中的误差的存在。

公开(公告)号：US08972664B2

公开(公告)日：2015-03-03

申请号：US13793708

申请日：2013-03-11

Applicant: International Business Machines Corporation

Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Michael A. Blake ,  Craig R. Walters ,  Pak-Kin Mak

IPC: G06F12/06 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0811 ,  G06F12/0817 ,  G06F12/0884 ,  G06F12/123

Abstract: Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.

Abstract translation: 实施例涉及在具有系统存储器的多级缓存系统上访问高速缓存行。 基于本地节点对特定高速缓存线的独占所有权的请求，请求被本地节点同时发送到用于特定高速缓存行的多个节点的系统内存和远程节点。 在特定的远程节点中找到特定的高速缓存行。 特定的远程节点是远程节点之一。 从特定的远程节点中删除特定的高速缓存行以供另一个节点独占所有。 基于具有指定缓存行在幽灵状态的指定节点，任何后续的提取请求将针对具体的缓存行启动，特定的缓存行遇到幽灵状态。 当遇到鬼状态时，后续的提取请求仅被引导到多个节点的节点。

公开(公告)号：US20130339609A1

公开(公告)日：2013-12-19

申请号：US13793708

申请日：2013-03-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Michael A. Blake ,  Craig R. Walters ,  Pak-Kin Mak

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0817 ,  G06F12/0884 ,  G06F12/123

Abstract: Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.

Abstract translation: 实施例涉及在具有系统存储器的多级缓存系统上访问高速缓存行。 基于本地节点对特定高速缓存线的独占所有权的请求，请求被本地节点同时发送到用于特定高速缓存行的多个节点的系统内存和远程节点。 在特定的远程节点中找到特定的高速缓存行。 特定的远程节点是远程节点之一。 从特定的远程节点中删除特定的高速缓存行以供另一个节点独占所有。 基于具有指定缓存行在幽灵状态的指定节点，任何后续的提取请求将针对具体的缓存行启动，特定的缓存行遇到幽灵状态。 当遇到鬼状态时，后续的提取请求仅被引导到多个节点的节点。

公开(公告)号：US10572385B2

公开(公告)日：2020-02-25

申请号：US15836154

申请日：2017-12-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Pak-Kin Mak ,  Vesselina K. Papazova ,  Hanno Ulrich

IPC: G06F12/0815 ,  G06F12/14 ,  G06F12/0813 ,  G06F12/0831

Abstract: A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a cache line of the cache. The node is in one region of nodes of a plurality of regions of nodes. The one region of nodes includes the node requesting exclusive access and another node of the computing environment, in which the node and the another node are local to one another as defined by a predetermined criteria. The node requesting exclusive access checks a locality cache coherency state of the another node, the locality cache coherency state being specific to the another node and indicating whether the another node has access to the cache line. Based on the checking indicating that the another node has access to the cache line, a determination is made that the node requesting exclusive access is to be granted exclusive access to the cache line. The determining being independent of transmission of information relating to the cache line from one or more other nodes of the one or more other regions of nodes.

公开(公告)号：US10528253B2

公开(公告)日：2020-01-07

申请号：US14533579

申请日：2014-11-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ekaterina M. Ambroladze ,  Garrett M. Drapala ,  Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Gary E. Strait

IPC: G06F3/06 ,  G06F12/0842 ,  G06F13/42

Abstract: A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.

公开(公告)号：US10042554B2

公开(公告)日：2018-08-07

申请号：US14946015

申请日：2015-11-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ekaterina M. Ambroladze ,  Garrett M. Drapala ,  Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Gary E. Strait

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0842 ,  G06F13/42

Abstract: A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.

公开(公告)号：US20180101474A1

公开(公告)日：2018-04-12

申请号：US15836154

申请日：2017-12-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Pak-Kin Mak ,  Vesselina K. Papazova ,  Hanno Ulrich

IPC: G06F12/0815 ,  G06F12/0831 ,  G06F12/0813 ,  G06F12/14

CPC classification number: G06F12/0815 ,  G06F12/0813 ,  G06F12/0835 ,  G06F12/1416 ,  G06F2212/314 ,  G06F2212/50 ,  G06F2212/621 ,  G06F2212/622

Abstract: A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a cache line of the cache. The node is in one region of nodes of a plurality of regions of nodes. The one region of nodes includes the node requesting exclusive access and another node of the computing environment, in which the node and the another node are local to one another as defined by a predetermined criteria. The node requesting exclusive access checks a locality cache coherency state of the another node, the locality cache coherency state being specific to the another node and indicating whether the another node has access to the cache line. Based on the checking indicating that the another node has access to the cache line, a determination is made that the node requesting exclusive access is to be granted exclusive access to the cache line. The determining being independent of transmission of information relating to the cache line from one or more other nodes of the one or more other regions of nodes.

公开(公告)号：US09858190B2

公开(公告)日：2018-01-02

申请号：US14606432

申请日：2015-01-27

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Timothy C. Bronson ,  Garrett M. Drapala ,  Michael Fee ,  Matthias Klein ,  Pak-kin Mak ,  Robert J. Sonnelitter, III ,  Gary E. Strait

IPC: G06F12/08 ,  G06F12/0855 ,  G06F12/0831

CPC classification number: G06F12/0855 ,  G06F12/0833 ,  G06F2212/1021 ,  G06F2212/608 ,  G06F2212/621

Abstract: Maintaining store order with high throughput in a distributed shared memory system. A request is received for a first ordered data store and a coherency check is initiated. A signal is sent that pipelining of a second ordered data store can be initiated. If a delay condition is encountered during the coherency check for the first ordered data store, rejection of the first ordered data store is signaled. If a delay condition is not encountered during the coherency check for the first ordered data store, a signal is sent indicating a readiness to continue pipelining of the second ordered data store.

公开(公告)号：US09678873B2

公开(公告)日：2017-06-13

申请号：US14621460

申请日：2015-02-13

Applicant: International Business Machines Corporation

Inventor： Garrett M. Drapala ,  Vesselina K. Papazova ,  Robert J. Sonnelitter, III

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084

CPC classification number: G06F12/0833 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084 ,  G06F12/0893 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/621

Abstract: In one embodiment, a computer-implemented method includes detecting a cache miss for a cache line. A resource is reserved on each of one or more remote computing nodes, responsive to the cache miss. A request for a state of the cache line on the one or more remote computing nodes is broadcast to the one or more remote computing nodes, responsive to the cache miss. A resource credit is received from a first remote computing node of the one or more remote computing nodes, responsive to the request. The resource credit indicates that the first remote computing node will not participate in completing the request. The resource on the first remote computing node is released, responsive to receiving the resource credit from the first remote computing node.

公开(公告)号：US20160232099A1

公开(公告)日：2016-08-11

申请号：US14616784

申请日：2015-02-09

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Deanna P. Berger ,  Garrett M. Drapala ,  Michael Fee ,  Pak-kin Mak ,  Arthur J. O'Neill, JR. ,  Diana L. Orf

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0868 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G06F11/10 ,  G06F11/1446 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/311 ,  G06F2212/60 ,  G06F2212/608

Abstract: In an approach for backing up designated data located in a cache, data stored within an index of a cache is identified, wherein the data has an associated designation indicating that the data is applicable to be backed up to a higher level memory. It is determined that the data stored to the cache has been updated. A status associated with the data is adjusted, such that the adjusted status indicates that the data stored to the cache has not been changed. A copy of the data is created. The copy of the data is stored to the higher level memory.

Abstract translation: 在用于备份位于高速缓存中的指定数据的方法中，识别存储在高速缓存的索引内的数据，其中数据具有指示该数据可应用于备份到较高级存储器的相关联的指定。 确定存储到高速缓存的数据已被更新。 调整与数据相关联的状态，使得调整状态指示存储到高速缓存的数据未被改变。 创建数据的副本。 数据的副本存储到较高级别的内存。