公开(公告)号：US09819479B2

公开(公告)日：2017-11-14

申请号：US14868834

申请日：2015-09-29

Applicant: Intel IP Corporation

Inventor： Ofir Degani ,  Rotem Banin ,  Sebastian Sievert

IPC: H04L27/36 ,  H04L7/00 ,  H03F3/24 ,  H03M1/68 ,  H03F3/217 ,  H03M1/82

CPC classification number: H04L7/002 ,  H03F3/2178 ,  H03F3/245 ,  H03M1/68 ,  H03M1/82 ,  H04L7/0091 ,  H04L27/365

Abstract: Described herein are technologies related to an implementation of a digital-to-time converter (DTC) circuitry that utilizes a first interpolation and a second and finer interpolation to increase interpolation ranges. The DTC circuitry generates a fine-phase modulated signal generating at least two correlated signals, and generating coarse and fine interpolations of the correlated signals.

公开(公告)号：US10972085B2

公开(公告)日：2021-04-06

申请号：US15811730

申请日：2017-11-14

Applicant: Intel IP Corporation

Inventor： Sebastian Sievert ,  Sarit Zur ,  Ofir Degani ,  Rotem Banin

IPC: H03K5/151 ,  H03K5/131 ,  H03K5/00 ,  H03M1/68 ,  H03M1/82

Abstract: A phase interpolator is provided. The phase interpolator includes a plurality of first interpolation cells each configured to supply a first current to a common node of the phase interpolator. Further, the phase interpolator includes a plurality of second interpolation cells each configured to supply a second current to the common node. The second current is lower than the first current, wherein a sum of the plurality of second currents supplied to the common node by the plurality of second interpolation cells is substantially equal to the first current.

公开(公告)号：US10477476B2

公开(公告)日：2019-11-12

申请号：US15280350

申请日：2016-09-29

Applicant: Intel IP Corporation

Inventor： Michael Kerner ,  Uri Perlmutter ,  Avishay Friedman ,  Rotem Banin ,  Tzvi Maimon

IPC: H04W52/02 ,  H04L5/00 ,  H04W76/27 ,  H04L27/26

Abstract: A wireless device and method of power consumption reduction are generally described herein. The wireless device may map a plurality of data symbols to sub-carriers for an orthogonal frequency division multiplexing (OFDM) transmission. The wireless device may divide the plurality of data symbols into first and second groups of data symbols. The wireless device may generate a first OFDM signal from the first group of data symbols for amplification by a first power amplifier (PA). The wireless device may generate a second OFDM signal from the second group of data symbols for amplification by a second PA. The data symbols of the first and second groups may be selected to provide a PAPR of the first OFDM signal that is lower than a PAPR of a composite OFDM signal based on the plurality of data symbols.

公开(公告)号：US20190052279A1

公开(公告)日：2019-02-14

申请号：US16077087

申请日：2017-01-24

Applicant: Intel IP Corporation

Inventor： Elan Banin ,  Tamar Marom ,  Gil Horovitz ,  Rotem Banin

IPC: H03L7/091

Abstract: A circuit is configured to reduce a noise component of a measured phase signal. The circuit includes an input for a phase signal of an oscillator and an error signal estimator configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit further includes a combiner configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.

公开(公告)号：US20180175842A1

公开(公告)日：2018-06-21

申请号：US15811730

申请日：2017-11-14

Applicant: Intel IP Corporation

Inventor： Sebastian Sievert ,  Sarit Zur ,  Ofir Degani ,  Rotem Banin

IPC: H03K5/151

CPC classification number: H03K5/1515 ,  H03K5/131 ,  H03K2005/00052 ,  H03M1/687 ,  H03M1/82

Abstract: A phase interpolator is provided. The phase interpolator includes a plurality of first interpolation cells each configured to supply a first current to a common node of the phase interpolator. Further, the phase interpolator includes a plurality of second interpolation cells each configured to supply a second current to the common node. The second current is lower than the first current, wherein a sum of the plurality of second currents supplied to the common node by the plurality of second interpolation cells is substantially equal to the first current.

公开(公告)号：US09735952B2

公开(公告)日：2017-08-15

申请号：US14861132

申请日：2015-09-22

Applicant: Intel IP Corporation

Inventor： Ashoke Ravi ,  Ofir Degani ,  Rotem Banin ,  Assaf Ben-Bassat

IPC: H04B15/00 ,  H04L7/04 ,  H04L7/00 ,  H04B1/04 ,  G04F10/00 ,  H03K5/135 ,  H03M1/10 ,  H03M1/82

CPC classification number: H04L7/042 ,  G04F10/005 ,  H03K5/135 ,  H03M1/1061 ,  H03M1/82 ,  H04B1/0475 ,  H04L7/0054

Abstract: A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction component. The DTC can receive one or more signals and a digital code to generate a modulation signal by controlling an offset of the one or more signals based on the digital code. The detector component can comprise a TDC or another DTC that operates to measure a dynamic behavior in response to detecting nonlinearities of the modulation signal. The distortion correction component can generate a set of distortion data that removes the dynamic behavior from an output of the DTC based on the measurement.

公开(公告)号：US09641185B1

公开(公告)日：2017-05-02

申请号：US15199217

申请日：2016-06-30

Applicant: INTEL IP CORPORATION

Inventor： Georgios Yorgos Palaskas ,  Paolo Madoglio ,  Peter Preyler ,  Rotem Banin

IPC: H03M1/66 ,  H03M1/06 ,  H03M7/42 ,  H03M1/46

CPC classification number: H03M1/06 ,  H03F3/195 ,  H03F3/24 ,  H03M1/466 ,  H03M1/68 ,  H03M1/82 ,  H03M5/02 ,  H03M7/42

Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.

公开(公告)号：US09231602B1

公开(公告)日：2016-01-05

申请号：US14490115

申请日：2014-09-18

Applicant: Intel IP Corporation

Inventor： Elan Banin ,  Rotem Banin ,  Ofir Degani ,  Ran Shimon ,  Ashoke Ravi

IPC: H03L7/06 ,  H03L7/08 ,  G04F10/00

CPC classification number: G04F10/005 ,  H03L7/085 ,  H03L2207/50

Abstract: A digital phase locked loop operates with a time-to-digital converter and an a-priori-probability-phase-estimation component or estimator component that estimates the un-quantized phase associated with a quantization output of the time-to-digital converter. The time-to-digital converter generates a quantized value as the quantization output from a local oscillator signal of a local oscillator and a reference signal of a reference clock. The estimation component estimates a phase value from the quantized values as a function of a-priori data related to the time-to-digital converter and boundaries of the quantized value.

Abstract translation: 数字锁相环用时间数字转换器和估计与时间数字转换器的量化输出相关联的未量化相位的先验概率相位估计分量或估计器分量进行操作。 时间 - 数字转换器产生量化值作为本地振荡器的本地振荡器信号和参考时钟的参考信号的量化输出。 估计分量从作为与时间 - 数字转换器相关的先验数据和量化值的边界的函数的量化值估计相位值。