公开(公告)号：US10707880B2

公开(公告)日：2020-07-07

申请号：US16077087

申请日：2017-01-24

Applicant: Intel IP Corporation

Inventor： Elan Banin ,  Tamar Marom ,  Gil Horovitz ,  Rotem Banin

IPC: H03L7/091 ,  H03L7/085 ,  H04L7/033 ,  H04L7/04

Abstract: A circuit is configured to reduce a noise component of a measured phase signal. The circuit includes an input for a phase signal of an oscillator and an error signal estimator configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit further includes a combiner configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.

公开(公告)号：US20190052279A1

公开(公告)日：2019-02-14

申请号：US16077087

申请日：2017-01-24

Applicant: Intel IP Corporation

Inventor： Elan Banin ,  Tamar Marom ,  Gil Horovitz ,  Rotem Banin

IPC: H03L7/091

Abstract: A circuit is configured to reduce a noise component of a measured phase signal. The circuit includes an input for a phase signal of an oscillator and an error signal estimator configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit further includes a combiner configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.