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公开(公告)号：US20200235106A1
公开(公告)日：2020-07-23
申请号：US16251129
申请日：2019-01-18
发明人： Xinshu CAI , Shyue Seng TAN , Eng Huat TOH
IPC分类号： H01L27/112 , H01L27/115 , G11C17/16
摘要： An anti-fuse memory cell may include a substrate including first and second conductivity regions and an isolation region at least partially within the substrate, a program gate over the substrate, a program gate oxide layer over the isolation region and between the program gate and the substrate, a first channel region arranged laterally between the first conductivity region and the isolation region, a second channel region arranged laterally between the second conductivity region and the isolation region, a first select gate arranged over the substrate and over the first channel region and a second select gate arranged over the substrate and over the second channel region. The program gate oxide layer may be configured to break down to allow conduction between the program gate and at least one of the channel regions upon providing a program voltage difference between the program gate and at least one of the channel regions.
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公开(公告)号：US20200098769A1
公开(公告)日：2020-03-26
申请号：US16695445
申请日：2019-11-26
IPC分类号： H01L27/11521 , H01L29/423 , H01L27/1159 , H01L27/11558 , H01L29/788 , H01L49/02 , H01L27/11524 , H01L29/49 , H01L29/51 , H01L29/10 , H01L29/66 , H01L29/78 , H01L29/08 , H01L21/28
摘要： Devices and methods of forming a device are disclosed. The device includes a substrate defined with at least a device region. A multi-gate transistor disposed in the device region which includes first and second gates both having first and second gate sidewalls. The multi-gate transistor also includes first source/drain (S/D) regions disposed adjacent to the first gate sidewall of the first and second gate, a common second S/D region disposed adjacent to the second gate sidewall of the first and second gate. A negative capacitance element is disposed within the second gate to reduce total overlap capacitance of the transistor. An interlevel dielectric (ILD) layer is disposed over the substrate and covering the transistor. First and second contacts are disposed in the ILD layer which are coupled to the first and second S/D regions respectively.
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23.发明申请公开(公告)号：US20190378848A1
公开(公告)日：2019-12-12
申请号：US16001485
申请日：2018-06-06
IPC分类号： H01L27/11521 , H01L27/11519 , G11C16/04 , G11C16/10
摘要： A method of forming a low-cost and compact hybrid SOI and bulk MTP cell and the resulting devices are provided. Embodiments include forming a bulk region in a SOI wafer; forming an NW in the bulk region and a PW in a remaining SOI region of the SOI wafer; forming first and second pairs of common FG stacks over both of the SOI and bulk regions; forming a first shared N+ RSD between each common FG stack of the first and second pairs in a top Si layer; forming a N+ RSD in the top Si layer of the SOI region on an opposite side of each common FG stack from the first shared N+ RSD; forming a second shared N+ RSD between each common FG stack in the bulk region; and forming a P+ RSD between the first and second pairs in the bulk region.
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公开(公告)号：US20190088783A1
公开(公告)日：2019-03-21
申请号：US16195150
申请日：2018-11-19
IPC分类号： H01L29/78 , H01L29/66 , H01L21/84 , H01L23/525 , H01L27/112
CPC分类号： H01L29/7855 , H01L21/845 , H01L23/5252 , H01L27/11206 , H01L27/1211 , H01L29/66545 , H01L29/6656 , H01L29/66795
摘要： Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate having a BOX layer; forming fins on the BOX layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of a fin or both fins; forming a S/D region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a WL; utilizing each third gate as a SL or connecting a SL to the S/D region; and connecting a BL to the S/D region or the at least one third gate.
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公开(公告)号：US20180212058A1
公开(公告)日：2018-07-26
申请号：US15410848
申请日：2017-01-20
IPC分类号： H01L29/78 , H01L27/112 , H01L23/525 , H01L29/66 , H01L21/84
CPC分类号： H01L29/7855 , H01L21/845 , H01L23/5252 , H01L27/11206 , H01L29/66545 , H01L29/6656 , H01L29/66795
摘要： Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate having a BOX layer; forming fins on the BOX layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of a fin or both fins; forming a S/D region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a WL; utilizing each third gate as a SL or connecting a SL to the S/D region; and connecting a BL to the S/D region or the at least one third gate.
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公开(公告)号：US20180102178A1
公开(公告)日：2018-04-12
申请号：US15838340
申请日：2017-12-11
发明人： Ping ZHENG , Eng Huat TOH , Elgin Kiok Boone QUEK
IPC分类号： G11C17/14 , H01L45/00 , H01L27/112
CPC分类号： G11C17/14 , H01L27/11206 , H01L45/04 , H01L45/1206 , H01L45/146 , H01L45/165 , H01L45/1675
摘要： Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region.
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公开(公告)号：US20170288131A1
公开(公告)日：2017-10-05
申请号：US15470936
申请日：2017-03-28
CPC分类号： H01L43/065 , G01R33/0052 , G01R33/07 , H01L43/04 , H01L43/14
摘要： An integrated Hall effect sensor is disclosed. The integrated Hall effect sensor has high tunable sensitivity by varying the thickness of the Hall plate. The Hall effect sensor is integrated onto a crystalline-on-insulator substrate, such as silicon-on-insulator (SOI) substrate. The Hall plate is part of the surface substrate of the SOI substrate. A sensor well is disposed in the bulk substrate of the SOI substrate. By applying an appropriate well bias voltage, the thickness of the Hall plate can be tuned from below the surface substrate to achieve the desired sensitivity. A gate may also be provided on the surface substrate. Biasing the gate with an appropriate gate bias voltage can further enhance thickness tunability of the Hall plate from above to achieve the desired sensitivity.
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公开(公告)号：US20160225429A1
公开(公告)日：2016-08-04
申请号：US15012736
申请日：2016-02-01
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1657 , G11C11/1659 , G11C11/1673 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/12
摘要： Memory cells and methods for forming a memory cell are presented. The memory cell includes a storage unit and a selector unit. The storage unit includes a magnetic storage element with first and second storage terminals and a bitline coupled to the second storage terminal. The selector unit includes a first selector and a second selector. The first selector may be a tunneling select transistor or a metal oxide semiconductor select transistor. The second tunneling select transistor is configured to have a second unidirectional current flow between its source and drain terminals. The second selector serves at least as a read selector for read operations of the memory cell and a read current is in the direction of the second unidirectional current flow between the source drain terminals of the second selector.
摘要翻译： 介绍了存储单元和形成存储单元的方法。 存储单元包括存储单元和选择器单元。 存储单元包括具有第一和第二存储终端的磁存储元件和耦合到第二存储终端的位线。 选择器单元包括第一选择器和第二选择器。 第一选择器可以是隧穿选择晶体管或金属氧化物半导体选择晶体管。 第二隧道选择晶体管被配置为在其源极和漏极端子之间具有第二单向电流。 第二选择器至少用作存储单元的读取操作的读取选择器，并且读取电流在第二选择器的源极漏极之间的第二单向电流流动的方向上。
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公开(公告)号：US20160163724A1
公开(公告)日：2016-06-09
申请号：US15015111
申请日：2016-02-03
发明人： Shyue Seng TAN , Eng Huat TOH
IPC分类号： H01L27/115 , H01L29/788 , H01L29/423
CPC分类号： H01L27/11524 , H01L27/11521 , H01L27/2436 , H01L29/42328 , H01L29/66825 , H01L29/788 , H01L45/1226 , H01L45/126 , H01L45/1608 , H01L45/1691
摘要： Devices and methods for forming a device are disclosed. The method includes providing a substrate and forming a memory cell pair on the substrate. Each of a memory cell of the memory cell pair includes at least one transistor having first and second gates formed between first and second terminals and a third gate disposed over the second terminal. The first gate serves as an access gate (AG), the second gate serves as a storage gate and the third gate serves as an erase gate (EG). The first cell terminal serves as a bitline terminal and the second cell terminal serves as a source line terminal. The source line terminal is a raised source line terminal and is elevated with respect to the bit line terminal and the source line terminal is common to the memory cell pair.
摘要翻译： 公开了用于形成装置的装置和方法。 该方法包括提供衬底并在衬底上形成存储单元对。 存储单元对的存储单元中的每一个包括至少一个晶体管，其具有形成在第一和第二端子之间的第一和第二栅极以及设置在第二端子上的第三栅极。 第一栅极用作接入门（AG），第二栅极用作存储栅极，第三栅极用作擦除栅极（EG）。 第一小区终端用作位线终端，第二小区终端用作源线路终端。 源极端子是升高的源极线端子，并且相对于位线端子升高，并且源极线端子对于存储器单元对是共同的。
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公开(公告)号：US20150325697A1
公开(公告)日：2015-11-12
申请号：US14713819
申请日：2015-05-15
发明人： Eng Huat TOH , Jae Gon LEE , Chung Foong TAN , Elgin QUEK
IPC分类号： H01L29/78 , H01L29/51 , H01L29/49 , H01L29/423 , H01L29/06
CPC分类号： H01L29/7816 , H01L29/42364 , H01L29/42368 , H01L29/42372 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66681
摘要： An LDMOS is formed with a second gate stack over n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include a device including a substrate; a first well and a second well in the substrate, the first well being doped with a first conductivity type dopant, the second well being doped with a second conductivity type dopant, and the second well surrounding the first well; a source in the first well and a drain in the second well; a doped region of the first conductivity type dopant in the first well, the doped region functioning as a body contact to the first well; a first gate stack on a portion of the first well; a second gate stack on a portion of the second well, the first and second gate stacks having a common gate electrode.
摘要翻译： LDMOS由n-漂移区上的第二栅极堆叠形成，具有与栅极堆叠相同的公共栅电极，并具有比栅叠层更高的功函数。 实施例包括：包括基板的装置; 在衬底中的第一阱和第二阱，所述第一阱掺杂有第一导电类型的掺杂剂，所述第二阱掺杂有第二导电型掺杂剂，所述第二阱围绕所述第一阱; 第一口井的源头和第二口井的排水沟; 所述第一阱中的所述第一导电类型掺杂剂的掺杂区域，所述掺杂区域用作与所述第一阱的体接触; 在第一井的一部分上的第一栅极堆叠; 在第二阱的一部分上的第二栅极堆叠，第一和第二栅极堆叠具有公共栅电极。
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