公开(公告)号：US20250080126A1

公开(公告)日：2025-03-06

申请号：US18460259

申请日：2023-09-01

Applicant: Apple Inc.

Inventor： Long Kong ,  Shinan Lu ,  Utku Seckin

IPC: H03M1/06 ,  G06F17/14 ,  H03M1/08

Abstract: The present disclosure relates to compensating for temperature variation of a mixer. Embodiments herein may include performing a single-point Fast Fourier Transform (FFT) (or complex downconversion with DC average) for a number of samples to obtain a transform for each of the number of samples, phase aligning a set of phases associated with each transform, and averaging each transform to generate an analog-to-digital converter (ADC) power value. Further, the disclosed embodiments may include generating a compensation value based on the analog-to-digital converter power value and applying the compensation value to the calibration circuit of the mixer to compensate for a second-order intermodulation product.

公开(公告)号：US20230378988A1

公开(公告)日：2023-11-23

申请号：US17749987

申请日：2022-05-20

Applicant: Apple Inc.

Inventor： Linxiao Zhang ,  Utku Seckin ,  Vikram Magoon

IPC: H04B1/18

CPC classification number: H04B1/18

Abstract: This disclosure is directed to a radio frequency front end circuit with improved receiver. The radio frequency front end circuit may include one or more antennas coupled directly to a mixer of the receiver. The mixer may include sampling circuitry to provide sampled signals based on receiving received signals from the one or more antennas. For example, the mixer may provide the sampled signals to a low noise amplifier (LNA) or other downstream components for further processing and/or conditioning. In some cases, the sampling circuitry may include a number of sampling circuits each sampling a portion of a received signal. Moreover, in specific cases, each of the sampling circuits may couple to an impedance matching circuit based on an impedance of the one or more antennas. The mixer may also include various filtering circuits.

公开(公告)号：US11664766B2

公开(公告)日：2023-05-30

申请号：US17845666

申请日：2022-06-21

Applicant: Apple Inc.

Inventor： Feng Zhao ,  Utku Seckin

IPC: H04B1/26 ,  H03D7/14 ,  H04B15/00 ,  H03B5/12 ,  H04B1/10

CPC classification number: H03D7/1466 ,  H03B5/1265 ,  H03D7/1458 ,  H04B1/10 ,  H04B15/005

Abstract: An electronic device may include wireless circuitry with a baseband processor, a transceiver, a front-end module, and an antenna. The transceiver may include mixer circuitry. The mixer circuitry may include switches controlled by oscillator signals. The mixer circuitry may also include oscillator phase noise cancelling capacitors controlled by inverted oscillator signals. Operated in this way, the mixer circuitry exhibits improved noise figure performance.

公开(公告)号：US11481224B2

公开(公告)日：2022-10-25

申请号：US16557357

申请日：2019-08-30

Applicant: Apple Inc.

Inventor： Tao Mai ,  Robert G. Lorenz ,  Joachim S. Hammerschmidt ,  Utku Seckin

IPC: G06F9/38 ,  G06F9/30 ,  G06F17/16 ,  G06F1/08 ,  H03H17/02 ,  H03H17/06

Abstract: A digital filter according to the disclosure includes a processing circuit having a memory and a number of parallel processing circuits. The parallel processing circuits perform a convolution operations based on input data and function data that is accessed from the memory. The filter further includes a serializer for serializing data that is received from the processing circuits. A clock generator circuit provides a first clock signal to the processing circuit and a second clock signal to the serializer. The frequency of the second clock signal is greater than that of the first clock signal.

公开(公告)号：US11057009B2

公开(公告)日：2021-07-06

申请号：US16551618

申请日：2019-08-26

Applicant: Apple Inc.

Inventor： Utku Seckin ,  Hanwen Yang

IPC: H03F3/217 ,  H04B1/04 ,  H03K19/20 ,  H03K5/00 ,  H03K5/135

Abstract: A switching power amplifier includes logic circuitry that generates first and second components of a differential signal, based on received amplitude code and a delayed version of the same. The amplitude code includes a sign and a magnitude. When the sign is positive, a first logic path is configured to generate the first component based on the received amplitude code and the second logic path is configured to generate the second component based on the delayed amplitude code. When the sign is negative, the first logic path is configured to generate the first component based on the delayed amplitude code and the second logic path is configured to generate the second component based on the received amplitude code. The switching power amplifier further includes a differential-to-single ended conversion circuit configured to generate a single-ended signal based on the differential signal.

公开(公告)号：US10804912B2

公开(公告)日：2020-10-13

申请号：US16057807

申请日：2018-08-07

Applicant: Apple Inc.

Inventor： Utku Seckin ,  Simone Gambini ,  Benjamin W. Cook

IPC: H03L7/185 ,  H03K5/135 ,  H03L7/18 ,  H03L7/089 ,  H03L7/093

Abstract: A non-integer divider for dividing the frequency of a signal is disclosed. A non-integer divider includes a first divider that divides the frequency of a first signal. A mixer is coupled to receive the first signal, and a second signal having a frequency equivalent to that output by the first divider. The mixer outputs a third signal having a frequency based on respective frequencies of the first and second signal. A second divider receives and frequency divides the third signal to produce a fourth signal. A ratio of the frequency of the first signal to the fourth signal is a non-integer value.