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    Mixer Circuitry With Noise Cancellation
    1.
    发明申请
    Mixer Circuitry With Noise Cancellation 有权

    公开(公告)号：US20220321058A1

    公开(公告)日：2022-10-06

    申请号：US17845666

    申请日：2022-06-21

    Applicant: Apple Inc.

    Inventor： Feng Zhao ,  Utku Seckin

    IPC: H03D7/14 ,  H04B15/00 ,  H03B5/12 ,  H04B1/10

    Abstract: An electronic device may include wireless circuitry with a baseband processor, a transceiver, a front-end module, and an antenna. The transceiver may include mixer circuitry. The mixer circuitry may include switches controlled by oscillator signals. The mixer circuitry may also include oscillator phase noise cancelling capacitors controlled by inverted oscillator signals. Operated in this way, the mixer circuitry exhibits improved noise figure performance.

    Mixer Circuitry With Noise Cancellation
    2.
    发明申请
    Mixer Circuitry With Noise Cancellation 有权

    公开(公告)号：US20220094304A1

    公开(公告)日：2022-03-24

    申请号：US17348414

    申请日：2021-06-15

    Applicant: Apple Inc.

    Inventor： Feng Zhao ,  Utku Seckin

    IPC: H03D7/14 ,  H04B1/10 ,  H04B15/00 ,  H03B5/12

    Abstract: An electronic device may include wireless circuitry with a baseband processor, a transceiver, a front-end module, and an antenna. The transceiver may include mixer circuitry. The mixer circuitry may include switches controlled by oscillator signals. The mixer circuitry may also include oscillator phase noise cancelling capacitors controlled by inverted oscillator signals. Operated in this way, the mixer circuitry exhibits improved noise figure performance.

    Clock divider circuit with synchronized switching
    4.
    发明授权
    Clock divider circuit with synchronized switching 有权
    时钟分频电路同步切换

    公开(公告)号：US09306574B1

    公开(公告)日：2016-04-05

    申请号：US14638284

    申请日：2015-03-04

    Applicant: Apple Inc.

    Inventor： Feng Zhao ,  Raman S. Thiara

    IPC: H03K21/00 ,  H03K23/00 ,  H03K25/00 ,  H03K21/02 ,  H03K3/037 ,  H03L7/00

    CPC classification number: H03K21/026 ,  H03K21/10 ,  H03L7/00

    Abstract: The clock divider circuit includes a dividing circuit, a selection circuit, and a synchronization circuit. The dividing circuit is configured to receive an input clock signal at a first frequency, and to produce a number of different periodic signals based thereon. The selection circuit is configured to receive various ones of the periodic signals. An output clock signal may be provided from the selection circuit based on a selection made therein. The input clock signal may have a frequency that is an integer multiple of the output clock frequency. The selection circuit is configured to provide the output clock signal at different, selectable frequencies. The synchronization circuit may control the timing of the switching of the output clock signal from one frequency to the next so that such switching may be performed without glitches.

    Abstract translation: 时钟分频电路包括分频电路，选择电路和同步电路。 分频电路被配置为以第一频率接收输入时钟信号，并且基于此产生多个不同的周期信号。 选择电路被配置为接收各种周期信号。 可以基于其中进行的选择从选择电路提供输出时钟信号。 输入时钟信号可以具有作为输出时钟频率的整数倍的频率。 选择电路被配置为以不同的可选频率提供输出时钟信号。 同步电路可以控制从一个频率到下一个频率的输出时钟信号的切换的定时，使得可以在没有毛刺的情况下执行这种切换。

    Digital linearization technique for charge pump based fractional phased-locked loop
    6.
    发明授权
    Digital linearization technique for charge pump based fractional phased-locked loop 有权

    公开(公告)号：US10291243B2

    公开(公告)日：2019-05-14

    申请号：US15960523

    申请日：2018-04-23

    Applicant: Apple Inc.

    Inventor： Robert K. Kong ,  Feng Zhao ,  Wei Deng

    IPC: H03L7/197 ,  H03L7/089 ,  H03L7/183 ,  H03L7/191 ,  H03L7/099

    Abstract: An apparatus includes an oscillator, a frequency divider, a phase circuit, a charge pump, and a filter. The frequency divider may generate an early feedback signal using a clock signal, and may assert a feedback signal a number of periods of the clock signal after asserting the early feedback signal. The phase circuit may generate a charge control signal using a reference clock signal and the feedback signal, and may generate a discharge control signal using the early feedback signal, the reference clock signal, and the feedback signal. The charge pump may charge or discharge a circuit node using the charge control signal and the discharge control signal to generate a frequency control signal. The filter circuit may attenuate at least one frequency component of the frequency control signal. The oscillator circuit may modify a frequency of the clock signal using the frequency control signal.

    Mixer circuitry with noise cancellation
    9.
    发明授权
    Mixer circuitry with noise cancellation 有权

    公开(公告)号：US11095252B1

    公开(公告)日：2021-08-17

    申请号：US17026056

    申请日：2020-09-18

    Applicant: Apple Inc.

    Inventor： Feng Zhao ,  Utku Seckin

    IPC: H04B1/26 ,  H03D7/14 ,  H04B15/00 ,  H03B5/12 ,  H04B1/10

    Abstract: An electronic device may include wireless circuitry with a baseband processor, a transceiver, a front-end module, and an antenna. The transceiver may include mixer circuitry. The mixer circuitry may include switches controlled by oscillator signals. The mixer circuitry may also include oscillator phase noise cancelling capacitors controlled by inverted oscillator signals. Operated in this way, the mixer circuitry exhibits improved noise figure performance.

    Quantization noise cancellation for fractional-N phased-locked loop
    10.
    发明授权
    Quantization noise cancellation for fractional-N phased-locked loop 有权

    公开(公告)号：US10211842B2

    公开(公告)日：2019-02-19

    申请号：US16102445

    申请日：2018-08-13

    Applicant: Apple Inc.

    Inventor： Feng Zhao ,  Wei Deng ,  Dennis M. Fischette, Jr.

    IPC: H03L7/06 ,  H03L7/091 ,  H03L7/099 ,  H03L7/089 ,  H03L7/197

    Abstract: A system includes an oscillator, a frequency divider, and a delay circuit. The oscillator may generate a clock signal using a reference signal. A frequency of the clock signal may be a non-integer multiple of a frequency of the reference signal. The frequency divider may generate a feedback signal using the clock signal and an adjustment factor based on the non-integer multiple. The delay circuit may select a particular delayed feedback signal from a plurality of delayed feedback signals based on a value of the adjustment factor. Each of the delayed feedback signals may be generated using periods of the clock signal. The delay circuit may also modify the particular delayed feedback signal using a portion of a period of the clock signal based on the adjustment factor. The oscillator may also adjust the frequency of the clock signal using the reference signal and the particular delayed feedback signal.

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