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公开(公告)号：US10211842B2
公开(公告)日：2019-02-19
申请号：US16102445
申请日：2018-08-13
Applicant: Apple Inc.
Inventor： Feng Zhao , Wei Deng , Dennis M. Fischette, Jr.
Abstract: A system includes an oscillator, a frequency divider, and a delay circuit. The oscillator may generate a clock signal using a reference signal. A frequency of the clock signal may be a non-integer multiple of a frequency of the reference signal. The frequency divider may generate a feedback signal using the clock signal and an adjustment factor based on the non-integer multiple. The delay circuit may select a particular delayed feedback signal from a plurality of delayed feedback signals based on a value of the adjustment factor. Each of the delayed feedback signals may be generated using periods of the clock signal. The delay circuit may also modify the particular delayed feedback signal using a portion of a period of the clock signal based on the adjustment factor. The oscillator may also adjust the frequency of the clock signal using the reference signal and the particular delayed feedback signal.
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公开(公告)号：US20180351561A1
公开(公告)日：2018-12-06
申请号：US16102445
申请日：2018-08-13
Applicant: Apple Inc.
Inventor： Feng Zhao , Wei Deng , Dennis M. Fischette, JR.
CPC classification number: H03K5/135 , H03L7/081 , H03L7/1976
Abstract: A system includes an oscillator, a frequency divider, and a delay circuit. The oscillator may generate a clock signal using a reference signal. A frequency of the clock signal may be a non-integer multiple of a frequency of the reference signal. The frequency divider may generate a feedback signal using the clock signal and an adjustment factor based on the non-integer multiple. The delay circuit may select a particular delayed feedback signal from a plurality of delayed feedback signals based on a value of the adjustment factor. Each of the delayed feedback signals may be generated using periods of the clock signal. The delay circuit may also modify the particular delayed feedback signal using a portion of a period of the clock signal based on the adjustment factor. The oscillator may also adjust the frequency of the clock signal using the reference signal and the particular delayed feedback signal.
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公开(公告)号：US20180241405A1
公开(公告)日：2018-08-23
申请号：US15960523
申请日：2018-04-23
Applicant: Apple Inc.
Inventor： Robert K. Kong , Feng Zhao , Wei Deng
CPC classification number: H03L7/1974 , H03L7/089 , H03L7/0891 , H03L7/099 , H03L7/183 , H03L7/191 , H03L7/1976
Abstract: An apparatus includes an oscillator, a frequency divider, a phase circuit, a charge pump, and a filter. The frequency divider may generate an early feedback signal using a clock signal, and may assert a feedback signal a number of periods of the clock signal after asserting the early feedback signal. The phase circuit may generate a charge control signal using a reference clock signal and the feedback signal, and may generate a discharge control signal using the early feedback signal, the reference clock signal, and the feedback signal. The charge pump may charge or discharge a circuit node using the charge control signal and the discharge control signal to generate a frequency control signal. The filter circuit may attenuate at least one frequency component of the frequency control signal. The oscillator circuit may modify a frequency of the clock signal using the frequency control signal.
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公开(公告)号：US09954542B1
公开(公告)日：2018-04-24
申请号：US15421884
申请日：2017-02-01
Applicant: Apple Inc.
Inventor： Robert K. Kong , Feng Zhao , Wei Deng
CPC classification number: H03L7/1974 , H03L7/089 , H03L7/0891 , H03L7/099 , H03L7/183 , H03L7/191 , H03L7/1976
Abstract: An apparatus includes an oscillator, a frequency divider, a phase circuit, a charge pump, and a filter. The frequency divider may generate an early feedback signal using a clock signal, and may assert a feedback signal a number of periods of the clock signal after asserting the early feedback signal. The phase circuit may generate a charge control signal using a reference clock signal and the feedback signal, and may generate a discharge control signal using the early feedback signal, the reference clock signal, and the feedback signal. The charge pump may charge or discharge a circuit node using the charge control signal and the discharge control signal to generate a frequency control signal. The filter circuit may attenuate at least one frequency component of the frequency control signal. The oscillator circuit may modify a frequency of the clock signal using the frequency control signal.
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公开(公告)号：US20180234099A1
公开(公告)日：2018-08-16
申请号：US15429948
申请日：2017-02-10
Applicant: Apple Inc.
Inventor： Feng Zhao , Wei Deng , Dennis M. Fischette, JR.
CPC classification number: H03L7/091 , H03L7/0891 , H03L7/099 , H03L7/1974
Abstract: A system includes an oscillator, a frequency divider, and a delay circuit. The oscillator may generate a clock signal using a reference signal. A frequency of the clock signal may be a non-integer multiple of a frequency of the reference signal. The frequency divider may generate a feedback signal using the clock signal and an adjustment factor based on the non-integer multiple. The delay circuit may select a particular delayed feedback signal from a plurality of delayed feedback signals based on a value of the adjustment factor. Each of the delayed feedback signals may be generated using periods of the clock signal. The delay circuit may also modify the particular delayed feedback signal using a portion of a period of the clock signal based on the adjustment factor. The oscillator may also adjust the frequency of the clock signal using the reference signal and the particular delayed feedback signal.
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Patent Agency Ranking
公开(公告)号：US20200350919A1
公开(公告)日：2020-11-05
申请号：US16401737
申请日：2019-05-02
Applicant: Apple Inc.
Inventor： Cristian Marcu , Feng Zhao , Wei Deng , Chunwei Chang , Robert K. Kong , Saeed Chehrazi
Abstract: In a computer system, a phase-locked loop circuit may generate a clock signal using a reference signal. The phase-locked loop circuit may include a programmable divider stage that includes multiple divider stages. When a frequency calibration is initiated on the phase-locked loop circuit, a control circuit may generate a pause signal in response to one or more of the divider stages reaching a particular logic state. The programmable divider stage may hold the one or more of the divider stages in the particular logic state using the pause signal.
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公开(公告)号：US10050634B1
公开(公告)日：2018-08-14
申请号：US15429948
申请日：2017-02-10
Applicant: Apple Inc.
Inventor： Feng Zhao , Wei Deng , Dennis M. Fischette, Jr.
Abstract: A system includes an oscillator, a frequency divider, and a delay circuit. The oscillator may generate a clock signal using a reference signal. A frequency of the clock signal may be a non-integer multiple of a frequency of the reference signal. The frequency divider may generate a feedback signal using the clock signal and an adjustment factor based on the non-integer multiple. The delay circuit may select a particular delayed feedback signal from a plurality of delayed feedback signals based on a value of the adjustment factor. Each of the delayed feedback signals may be generated using periods of the clock signal. The delay circuit may also modify the particular delayed feedback signal using a portion of a period of the clock signal based on the adjustment factor. The oscillator may also adjust the frequency of the clock signal using the reference signal and the particular delayed feedback signal.
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公开(公告)号：US09979405B1
公开(公告)日：2018-05-22
申请号：US15429481
申请日：2017-02-10
Applicant: Apple Inc.
Inventor： Wei Deng , Dennis M. Fischette, Jr. , Meei-Ling Chiang , Samed Maltabas
CPC classification number: H03L7/081 , H03L7/085 , H03L7/1976
Abstract: A digital PLL is disclosed. In one embodiment, the digital PLL includes a TDC coupled to receive a reference clock signal and feedback signal. The TDC includes a chain of serially-coupled delay elements. An oscillator in the PLL is configured to generate a periodic output signal. A divider is coupled to receive the periodic output signal and generate the feedback signal provided to the TDC. The digital PLL also includes a control circuit. During a phase-locking procedure, each of the serially-coupled delay elements is enabled for fast phase capture. However, once phase-lock has been detected by observing TDC output code, the control circuit is adaptively configured to disable all but a subset of the delay elements for saving power.
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公开(公告)号：US09838025B1
公开(公告)日：2017-12-05
申请号：US15233124
申请日：2016-08-10
Applicant: Apple Inc.
Inventor： Wei Deng , Dennis Fischette, Jr. , Gin Yee
CPC classification number: H03L7/0891 , H03L7/1072 , H03L7/1075 , H03L7/113 , H03L7/18
Abstract: An apparatus includes circuitry and an oscillator circuit that may be configured to generate a clock signal dependent upon a control signal. The circuitry may be configured to perform a frequency measurement of the clock signal. In response to a determination that the frequency of the clock signal is greater than a first threshold, the circuitry may also be configured to perform a phase comparison between a divided clock signal and a reference clock signal, and to adjust a value of the control signal such that the adjusted value depends upon a result of the comparison. In response to a determination that the frequency of the clock signal is less than the first threshold, the circuitry may be configured to adjust the value of the control signal such that the adjusted value depends upon a result of the measurement.
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公开(公告)号：US10291243B2
公开(公告)日：2019-05-14
申请号：US15960523
申请日：2018-04-23
Applicant: Apple Inc.
Inventor： Robert K. Kong , Feng Zhao , Wei Deng
Abstract: An apparatus includes an oscillator, a frequency divider, a phase circuit, a charge pump, and a filter. The frequency divider may generate an early feedback signal using a clock signal, and may assert a feedback signal a number of periods of the clock signal after asserting the early feedback signal. The phase circuit may generate a charge control signal using a reference clock signal and the feedback signal, and may generate a discharge control signal using the early feedback signal, the reference clock signal, and the feedback signal. The charge pump may charge or discharge a circuit node using the charge control signal and the discharge control signal to generate a frequency control signal. The filter circuit may attenuate at least one frequency component of the frequency control signal. The oscillator circuit may modify a frequency of the clock signal using the frequency control signal.
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