公开(公告)号：US09577771B1

公开(公告)日：2017-02-21

申请号：US15218923

申请日：2016-07-25

Applicant: Apple Inc.

Inventor： Navid Lashkarian ,  Saeed Chehrazi ,  Ali Parsa

IPC: H04L25/03 ,  H04B17/21 ,  H04B17/24

CPC classification number: H04B17/21 ,  H03F1/0227 ,  H03F1/0266 ,  H03F3/19 ,  H03F2200/102 ,  H03F2200/411 ,  H03F2200/451 ,  H03F2200/465 ,  H04B17/11 ,  H04B17/13 ,  H04B17/14 ,  H04B17/24

Abstract: Systems and method for improving operation of a radio frequency system are provided. One embodiment provides a radio frequency system that includes an amplifier device with a first data path and a second data path. Additionally, the radio frequency system includes a controller that instructs the radio frequency system to transmit a calibration signal, which includes a first portion that excites the first data path and a second portion that excites the second data path; determines time skew between the first and second data paths based at least in part on phase shift between a first sample of a feedback signal and the first portion, phase shift between a second sample of the feedback signal and the second portion, or both; and instructs the radio frequency system to adjust delay applied on the first data path, the second data path, or both based at least on the time skew.

Abstract translation: 提供了改善射频系统操作的系统和方法。 一个实施例提供一种射频系统，其包括具有第一数据路径和第二数据路径的放大器装置。 另外，射频系统包括指示射频系统发送校准信号的控制器，该校准信号包括激励第一数据路径的第一部分和激励第二数据路径的第二部分; 至少部分地基于反馈信号的第一采样与第一部分之间的相移，反馈信号的第二采样与第二部分之间的相移或两者，确定第一和第二数据路径之间的时间偏移; 并且至少基于时间偏差来指示射频系统调整应用于第一数据路径，第二数据路径或两者的延迟。

公开(公告)号：US20200350919A1

公开(公告)日：2020-11-05

申请号：US16401737

申请日：2019-05-02

Applicant: Apple Inc.

Inventor： Cristian Marcu ,  Feng Zhao ,  Wei Deng ,  Chunwei Chang ,  Robert K. Kong ,  Saeed Chehrazi

IPC: H03L7/18 ,  H03L7/089 ,  H03L7/093 ,  H03L7/099

Abstract: In a computer system, a phase-locked loop circuit may generate a clock signal using a reference signal. The phase-locked loop circuit may include a programmable divider stage that includes multiple divider stages. When a frequency calibration is initiated on the phase-locked loop circuit, a control circuit may generate a pause signal in response to one or more of the divider stages reaching a particular logic state. The programmable divider stage may hold the one or more of the divider stages in the particular logic state using the pause signal.