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公开(公告)号：US10693477B1
公开(公告)日：2020-06-23
申请号：US16360787
申请日：2019-03-21
Applicant: Apple Inc.
Inventor： Cristian Marcu
Abstract: An oscillator subsystem included in a phase-locked loop circuit of a computer system may include coarse and fine-tuning circuits. The coarse-tuning circuit may generate a coarse-tuning current based on a reference voltage, and the fine-tuning circuit may generate a fine-tuning current by combining respective currents generated by first and second complement current mirror circuits using a voltage level of a control signal. An oscillator circuit may generate a clock signal whose frequency is based on a combination of the coarse and fine-tuning circuits.
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公开(公告)号：US20210336624A1
公开(公告)日：2021-10-28
申请号：US16855828
申请日：2020-04-22
Applicant: Apple Inc.
Inventor： Long Kong , Simone Gambini , Cristian Marcu , Nachum M. Kanovsky
Abstract: A computer system may periodically calibrate an oscillator subsystem, which includes a voltage-controlled oscillator circuit configured to generate an oscillator signal using code signal. In response to activation of a calibration mode, an iterative calibration operation may be performed on the voltage-controlled oscillator circuit. In some cases, performing a given iteration of the calibration operation includes determining a value of the code signal using a number of pulses in the oscillator signal sampled during a particular time period, along with previous values of the code signal and a slope of an error function associated with the difference between a desired frequency and a current frequency of the oscillator signal. In other cases, iterations may employ variable sampling times with error handling, in order to decrease the duration of the calibration operation while maintaining a target accuracy.
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公开(公告)号：US20200350919A1
公开(公告)日：2020-11-05
申请号：US16401737
申请日：2019-05-02
Applicant: Apple Inc.
Inventor： Cristian Marcu , Feng Zhao , Wei Deng , Chunwei Chang , Robert K. Kong , Saeed Chehrazi
Abstract: In a computer system, a phase-locked loop circuit may generate a clock signal using a reference signal. The phase-locked loop circuit may include a programmable divider stage that includes multiple divider stages. When a frequency calibration is initiated on the phase-locked loop circuit, a control circuit may generate a pause signal in response to one or more of the divider stages reaching a particular logic state. The programmable divider stage may hold the one or more of the divider stages in the particular logic state using the pause signal.
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公开(公告)号：US11139817B1
公开(公告)日：2021-10-05
申请号：US16855828
申请日：2020-04-22
Applicant: Apple Inc.
Inventor： Long Kong , Simone Gambini , Cristian Marcu , Nachum M. Kanovsky
Abstract: A computer system may periodically calibrate an oscillator subsystem, which includes a voltage-controlled oscillator circuit configured to generate an oscillator signal using code signal. In response to activation of a calibration mode, an iterative calibration operation may be performed on the voltage-controlled oscillator circuit. In some cases, performing a given iteration of the calibration operation includes determining a value of the code signal using a number of pulses in the oscillator signal sampled during a particular time period, along with previous values of the code signal and a slope of an error function associated with the difference between a desired frequency and a current frequency of the oscillator signal. In other cases, iterations may employ variable sampling times with error handling, in order to decrease the duration of the calibration operation while maintaining a target accuracy.
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