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公开(公告)号：US20230388100A1
公开(公告)日：2023-11-30
申请号：US18152492
申请日：2023-01-10
Applicant: Apple Inc.
Inventor： Hairong Yu , Boon-Aik Ang , Yu Chen , Litesh Sajnani , Samed Maltabas , Shaobo Liu , Gregory N. Santos , Richard Y. Su , Meei-Ling Chiang , Pyoungwon Park , Dennis M. Fischette, JR.
CPC classification number: H04L7/0337 , H04L7/0331 , H03L7/093
Abstract: A clock generator circuit may include a multiplex circuit and a phase-locked loop circuit. The multiplex circuit may generate a reference clock signal for the phase-locked loop circuit by selecting one of different clock signals. In response to a switch of the reference clock signal from one clock signal to another, the phase-locked loop circuit may disable phase-locking and enter into a frequency acquisition mode during which the frequency of the phase-locked loop circuit's output clock signal is adjusted based on the frequency of the newly selected reference clock signal. After a period of time has elapsed, the phase-locked loop circuit returns to phase-locking operation.
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Patent Agency Ranking
2.发明申请公开(公告)号：US20210167766A1
公开(公告)日：2021-06-03
申请号：US16701844
申请日：2019-12-03
Applicant: Apple Inc.
Inventor： Khaled M. Alashmouny , Dennis M. Fischette, JR. , Charles L. Wang , Samed Maltabas
Abstract: A system and method for efficient on-chip monitoring of clock signals post-silicon. An electronic circuit includes a post-silicon and on-die signal monitor and a first signal generator that sends a first signal with a first signal period to the signal monitor. The signal monitor selects a first sampling signal with a first sampling period such that a ratio of the first sampling period to the first signal period is greater than one and is a non-integer. The signal monitor selects a reference voltage level for indicating when the first signal is asserted. When the first sampling period has elapsed, the signal monitor samples the first signal to generate a voltage level, and upon completing sampling, determines a duty cycle of the generated voltage levels, which indicates a duty cycle of the first signal. Using a similar approach, the signal monitor is also capable of determining skew between two signals.
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3.发明申请公开(公告)号：US20210208621A1
公开(公告)日：2021-07-08
申请号：US16736776
申请日：2020-01-07
Applicant: Apple Inc.
Inventor： Meei-Ling Chiang , Dabin Zhang , Dennis M. Fischette, JR. , Shaobo Liu , Yu Chen , Samed Maltabas
IPC: G06F1/04
Abstract: Systems, apparatuses, and methods for implementing a hybrid asynchronous gray counter with a non-gray zone detector are described. A circuit includes an asynchronous gray counter coupled to control logic. The control logic programs the asynchronous gray counter to operate in different modes to perform various functions associated with a high-performance phase-locked loop (PLL). In a first mode, the asynchronous gray counter serves as a frequency detector to count oscillator cycles within a reference clock cycle. In a second mode, the asynchronous gray counter serves as a coarse phase detector to detect a phase error between a feedback clock and a reference clock. In a third mode, the asynchronous gray counter serves as a multi-modulus divider to divide an oscillator clock down to create a feedback clock. Using a single asynchronous gray counter for three separate functions reduces power consumption and area utilization.
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公开(公告)号：US20180351561A1
公开(公告)日：2018-12-06
申请号：US16102445
申请日：2018-08-13
Applicant: Apple Inc.
Inventor： Feng Zhao , Wei Deng , Dennis M. Fischette, JR.
CPC classification number: H03K5/135 , H03L7/081 , H03L7/1976
Abstract: A system includes an oscillator, a frequency divider, and a delay circuit. The oscillator may generate a clock signal using a reference signal. A frequency of the clock signal may be a non-integer multiple of a frequency of the reference signal. The frequency divider may generate a feedback signal using the clock signal and an adjustment factor based on the non-integer multiple. The delay circuit may select a particular delayed feedback signal from a plurality of delayed feedback signals based on a value of the adjustment factor. Each of the delayed feedback signals may be generated using periods of the clock signal. The delay circuit may also modify the particular delayed feedback signal using a portion of a period of the clock signal based on the adjustment factor. The oscillator may also adjust the frequency of the clock signal using the reference signal and the particular delayed feedback signal.
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公开(公告)号：US20240097672A1
公开(公告)日：2024-03-21
申请号：US17949454
申请日：2022-09-21
Applicant: Apple Inc.
Inventor： Yueming He , Dennis M. Fischette, JR.
IPC: H03K17/16 , H03K19/003
CPC classification number: H03K17/167 , H03K19/00361
Abstract: An integrated circuit may be provided with power switching circuitry. The power switching circuitry may include a primary power switch and multiple auxiliary power switches. A power gating control circuit may output control signals for selectively activating the primary power switch and at least one of the auxiliary power switches to charge a gated voltage. One or more voltage detectors may be configured to monitor the gated voltage and to activate the remaining auxiliary power switches in response to detecting that the gated voltage exceeds one or more thresholds. Configured and operated in this way, inrush current surge protection can be achieved while charging up the gated voltage sufficiently fast.
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公开(公告)号：US20180234099A1
公开(公告)日：2018-08-16
申请号：US15429948
申请日：2017-02-10
Applicant: Apple Inc.
Inventor： Feng Zhao , Wei Deng , Dennis M. Fischette, JR.
CPC classification number: H03L7/091 , H03L7/0891 , H03L7/099 , H03L7/1974
Abstract: A system includes an oscillator, a frequency divider, and a delay circuit. The oscillator may generate a clock signal using a reference signal. A frequency of the clock signal may be a non-integer multiple of a frequency of the reference signal. The frequency divider may generate a feedback signal using the clock signal and an adjustment factor based on the non-integer multiple. The delay circuit may select a particular delayed feedback signal from a plurality of delayed feedback signals based on a value of the adjustment factor. Each of the delayed feedback signals may be generated using periods of the clock signal. The delay circuit may also modify the particular delayed feedback signal using a portion of a period of the clock signal based on the adjustment factor. The oscillator may also adjust the frequency of the clock signal using the reference signal and the particular delayed feedback signal.
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