公开(公告)号：US20130024669A1

公开(公告)日：2013-01-24

申请号：US13625097

申请日：2012-09-24

Applicant: APPLE INC.

Inventor： Jeffry E. Gonion

IPC: G06F9/302

CPC classification number: G06F8/4441 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30072

Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions may also cause the processor to perform a shift operation on another input vector dependent upon the input vector and the control vector.

Abstract translation: 公开了一种系统和方法的实施例，其中处理器可以执行使处理器接收输入向量和控制向量的指令。 执行的指令还可以使处理器根据输入向量和控制向量对另一个输入向量执行移位操作。

公开(公告)号：US11972140B2

公开(公告)日：2024-04-30

申请号：US18069033

申请日：2022-12-20

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Jeffry E. Gonion ,  Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Gerard R. Williams, III

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1018 ,  G06F12/1045 ,  G06F13/16

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0683 ,  G06F12/0238 ,  G06F12/0646 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1018 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/1668

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

公开(公告)号：US20230418767A1

公开(公告)日：2023-12-28

申请号：US18343125

申请日：2023-06-28

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Bernard J. Semeria

IPC: G06F12/14 ,  G06F12/1027

CPC classification number: G06F12/1483 ,  G06F12/1027 ,  G06F12/1475

Abstract: A memory permissions model for a processor that is based on the memory address accessed by an instruction as well as the program counter of the instruction. These permissions may be stored in permissions tables and indexed using the memory addresses of the instruction and the address of the memory locations that it accesses. Those indexes may be obtained from a page table in some cases. These memory permissions may be used in conjunction with other permissions, such as execute permissions and secondary execution privileges that are based on whether the instruction belongs to a particular instruction group.

公开(公告)号：US20230058989A1

公开(公告)日：2023-02-23

申请号：US17821312

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Lior Zimet ,  Sergio Kolor ,  Sagi Lahav ,  James Vash ,  Gaurav Garg ,  Tal Kuzi ,  Jeffry E. Gonion ,  Charles E. Tucker ,  Lital Levy-Rubin ,  Dany Davidov ,  Steven Fishwick ,  Nir Leshem ,  Mark Pilip ,  Gerard R. Williams, III ,  Harshavardhan Kaushikkar ,  Srinivasan Rangan Sridharan

IPC: G06F12/0831 ,  G06F12/0811 ,  G06F12/128

Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.

公开(公告)号：US20230010948A1

公开(公告)日：2023-01-12

申请号：US17932883

申请日：2022-09-16

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Ian D. Kountanis ,  Conrado Blasco ,  Steven Andrew Myers ,  Yannick L. Sierra

IPC: G06F9/38 ,  G06F21/60 ,  G06F9/455 ,  G06F9/30

Abstract: A system and method for efficiently protecting branch prediction information. In various embodiments, a computing system includes at least one processor with a branch predictor storing branch target addresses and security tags in a table. The security tag includes one or more components of machine context. When the branch predictor receives a portion of a first program counter of a first branch instruction, and hits on a first table entry during an access, the branch predictor reads out a first security tag. The branch predictor compares one or more components of machine context of the first security tag to one or more components of machine context of the first branch instruction. When there is at least one mismatch, the branch prediction information of the first table entry is not used. Additionally, there is no updating of any branch prediction training information of the first table entry.

公开(公告)号：US10990401B2

公开(公告)日：2021-04-27

申请号：US16837631

申请日：2020-04-01

Applicant: Apple Inc.

Inventor： Tal Uliel ,  Eric Bainville ,  Jeffry E. Gonion ,  Ali Sazegari

IPC: G06F9/302 ,  G06F9/312 ,  G06F15/76 ,  G06F17/16 ,  G06F7/52 ,  G06F9/38 ,  G06F15/80 ,  G06F9/30 ,  G06F7/544

Abstract: In an embodiment, a computation engine may perform dot product computations on input vectors. The dot product operation may have a first operand and a second operand, and the dot product may be performed on a subset of the vector elements in the first operand and each of the vector elements in the second operand. The subset of vector elements may be separated in the first operand by a stride that skips one or more elements between each element to which the dot product operation is applied. More particularly, in an embodiment, the input operands of the dot product operation may be a first vector having second vectors as elements, and the stride may select a specified element of each second vector.

公开(公告)号：US10769065B2

公开(公告)日：2020-09-08

申请号：US16436635

申请日：2019-06-10

Applicant: Apple Inc.

Inventor： Ali Sazegari ,  Charles E. Tucker ,  Jeffry E. Gonion ,  Gerard R. Williams, III ,  Chris Cheng-Chieh Lee

IPC: H03M7/00 ,  G06F12/08 ,  H03M7/30 ,  G06F12/0886 ,  G06F12/00 ,  G06F13/00

Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.

公开(公告)号：US10592239B2

公开(公告)日：2020-03-17

申请号：US16423702

申请日：2019-05-28

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Tal Uliel ,  Erik Norden ,  Jeffry E. Gonion ,  Ali Sazegari

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38 ,  G06N3/04 ,  G06N3/063

Abstract: In an embodiment, a matrix computation engine is configured to perform matrix computations (e.g. matrix multiplications). The matrix computation engine may perform numerous matrix computations in parallel, in an embodiment. More particularly, the matrix computation engine may be configured to perform numerous multiplication operations in parallel on input matrix elements, generating resulting matrix elements. In an embodiment, the matrix computation engine may be configured to accumulate results in a result memory, performing multiply-accumulate operations for each matrix element of each matrix.

公开(公告)号：US20180121199A1

公开(公告)日：2018-05-03

申请号：US15629126

申请日：2017-06-21

Applicant: Apple Inc.

Inventor： Tal Uliel ,  Jeffry E. Gonion ,  Ali Sazegari ,  Eric Bainville

IPC: G06F9/30 ,  G06F7/483 ,  G06F7/485 ,  G06F7/487 ,  G06F7/544

CPC classification number: G06F9/30036 ,  G06F7/483 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/5443 ,  G06F9/30014

Abstract: In an embodiment, a processor may implement a fused multiply-add (FMA) instruction that accepts vector operands having vector elements with a first precision, and performing both the multiply and add operations at a higher precision. The add portion of the operation may add adjacent pairs of multiplication results from the multiply portion of the operation, which may allow the result to be stored in a vector register of the same overall length as the input vector registers but with fewer, higher precision vector elements, in an embodiment. Additionally, the overall operation may have high accuracy because of the higher precision throughout the operation.

公开(公告)号：US09632775B2

公开(公告)日：2017-04-25

申请号：US14177399

申请日：2014-02-11

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F3/00

CPC classification number: G06F9/30036 ,  G06F9/30043 ,  G06F9/345 ,  G06F9/3824 ,  G06F9/3836

Abstract: In an embodiment, a processor may include a completion time prediction circuit. The completion time prediction circuit may be configured to track one or more aspects of previous instances of a vector memory operation, and may be configured to predict a completion time for a current instance of the vector memory operation. The prediction may be used by the issue circuit to schedule operations dependent on the vector memory operation, if any.