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公开(公告)号：US20240258181A1
公开(公告)日：2024-08-01
申请号：US18160450
申请日：2023-01-27
CPC分类号： H01L23/13 , B32B3/02 , B32B9/005 , B32B9/041 , B32B15/20 , H01L21/4871 , H01L23/3735 , B32B2250/03 , B32B2250/40 , B32B2307/206 , B32B2457/00
摘要： Implementations of a substrate may include an electrically insulative layer having a first largest planar side and a second largest planar side opposing the first largest planar side; a first electrically conductive layer coupled to the first largest planar side and including a first scalloped edge having a first pattern; and a second electrically conductive layer coupled to the second largest planar side and including a second scalloped edge having a second pattern. The first pattern and the second pattern may alternate along at least one edge of the first largest planar side and at least one edge of the second largest planar side, respectively.
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公开(公告)号：US20240250042A1
公开(公告)日：2024-07-25
申请号：US18390928
申请日：2023-12-20
发明人： Seungwon IM , Oseob JEON
IPC分类号： H01L23/00 , H01L21/48 , H01L23/495
CPC分类号： H01L23/562 , H01L21/4839 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/50 , H01L24/86 , H01L2924/3512
摘要： In general aspect, a semiconductor device package can include a substrate and a semiconductor die disposed on and coupled with the substrate. The semiconductor device package can further include a leadframe having an indentation defined therein, at least a portion of the indentation being disposed on and coupled with the semiconductor die via a conductive adhesive.
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公开(公告)号：US20240242969A1
公开(公告)日：2024-07-18
申请号：US18619304
申请日：2024-03-28
IPC分类号： H01L21/306 , H01L21/308 , H01L21/66 , H01L29/20 , H01L29/66 , H01L29/78
CPC分类号： H01L21/30612 , H01L21/308 , H01L22/26 , H01L29/2003 , H01L29/66522 , H01L29/66666 , H01L29/7827
摘要： A method of manufacturing a vertical FET device includes providing a semiconductor substrate structure including a marker layer; forming a hardmask layer coupled to the semiconductor substrate structure, wherein the hardmask layer comprises a set of openings operable to expose an upper surface portion of the semiconductor substrate structure; etching the upper surface portion of the semiconductor substrate structure to form a plurality of fins; etching at least a portion of the marker layer; detecting the etching of the at least a portion of the marker layer; epitaxially growing a semiconductor layer in recess regions disposed between adjacent fins of the plurality of fins; forming a source metal layer on each of the plurality of fins; and forming a gate metal layer coupled to the semiconductor layer.
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公开(公告)号：US12040705B2
公开(公告)日：2024-07-16
申请号：US17817116
申请日：2022-08-03
发明人： Alexander Heubi
IPC分类号： H02M3/07
CPC分类号： H02M3/073
摘要： A high voltage is generated from a low supply voltage by a charge pump driven with a pulse generator. A comparator compares the low supply voltage to a predetermined proportion of the high voltage. A low power voltage divider creates the predetermined portion of the high voltage. The comparator output drives the pulse generator, and the pulse generator output resets the comparator. A high voltage to low voltage mode may also be employed using the same arrangement.
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公开(公告)号：US20240234246A1
公开(公告)日：2024-07-11
申请号：US18616351
申请日：2024-03-26
发明人： Seungwon IM , Oseob JEON , Byoungok LEE , Yoonsoo LEE , Joonseo SON , Dukyong LEE , Changyoung PARK
IPC分类号： H01L23/433 , H01L23/13 , H01L23/24 , H01L23/473 , H01L23/495 , H01L23/498 , H01L25/065
CPC分类号： H01L23/433 , H01L23/13 , H01L23/4334 , H01L23/473 , H01L23/49568 , H01L23/49861 , H01L25/0657 , H01L23/24 , H01L2224/33
摘要： Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.
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公开(公告)号：US12033904B2
公开(公告)日：2024-07-09
申请号：US17086932
申请日：2020-11-02
IPC分类号： H01L23/48 , H01L23/053 , H01L23/08 , H01L23/18 , H01L23/498
CPC分类号： H01L23/053 , H01L23/08 , H01L23/18 , H01L23/49811 , H01L2224/48091 , H01L2224/48227 , H01L2224/48091 , H01L2924/00014
摘要： Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate, and a plurality of press-fit pins. The plurality of press-fit pins may be fixedly coupled with the case. The plurality of press-fit pins may have at least one locking portion that extends from a side of the plurality of press-fit pins into the case and the plurality of press-fit pins may be electrically and mechanically coupled to the substrate.
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公开(公告)号：US12025814B2
公开(公告)日：2024-07-02
申请号：US18466555
申请日：2023-09-13
发明人： Koichi Abe
IPC分类号： H02P25/034 , G01P15/18 , G02B7/09 , G02B27/64 , H02P7/025
CPC分类号： G02B27/646 , G01P15/18 , G02B7/09 , H02P7/025
摘要： Various embodiments of the present technology may provide methods and systems for position stabilization. The methods and systems for position stabilization may be integrated within an electronic device. An exemplary system may include a driver circuit responsive to a gyro sensor and a feedback signal from an actuator. The driver circuit may be configured to calibrate a gain applied to a drive signal based on the posture of the electronic device.
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公开(公告)号：US20240213554A1
公开(公告)日：2024-06-27
申请号：US18146504
申请日：2022-12-27
发明人： Hideo KONDO
IPC分类号： H01M10/42 , G01R31/382 , G01R31/389 , G01R31/392
CPC分类号： H01M10/4285 , G01R31/382 , G01R31/389 , G01R31/392
摘要： A method, system, and integrated circuit are provided for monitoring a battery capacity within a battery backup system. A battery degradation profile is provided for a battery including first data associating operating temperature over accumulated time with second battery degradation data. The battery is kept charged in a failover battery backup circuit. The operating temperature of the battery is measured over time and third data is stored for the operating temperature over accumulated time. While the battery is operated in the backup system, the battery degradation profile is accessed based on the third data to obtain an associated battery degradation estimate. Responsive to the battery degradation estimate meeting a designated condition, the battery is electronically switched from operation to a test circuit, and the internal impedance of the battery is measured. Responsive to an unacceptable value of the internal impedance, an alert is issued.
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公开(公告)号：US20240205562A1
公开(公告)日：2024-06-20
申请号：US18067493
申请日：2022-12-16
摘要： An image sensor may include an array of imaging pixels arranged in rows and columns. Each imaging pixel may include a photodiode, an overflow capacitor, an overflow transistor that is interposed between the photodiode and the overflow capacitor, a floating diffusion region, a transfer transistor that is interposed between the photodiode and the floating diffusion region, a voltage supply, and a reset transistor that is interposed between the floating diffusion region and the voltage supply. The voltage supply may provide a voltage at a first magnitude that is less than the pinning voltage for a first portion of a reset period and may provide the voltage at a second magnitude that is greater than the pinning voltage for a second portion of the reset period.
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公开(公告)号：US20240204643A1
公开(公告)日：2024-06-20
申请号：US18068579
申请日：2022-12-20
CPC分类号： H02M1/0009 , H02M3/158
摘要： Current sensing in switching power converters. At least one example is a method comprising: discharging an inductor of a buck converter using a low-side FET during a discharge mode of a first cycle; providing, during the discharge mode, a signal indicative of instantaneous current to a voltage regulator, the signal indicative of instantaneous current proportional to current through the inductor during at least a portion of the discharge mode; charging the inductor using a high-side FET during a charge mode, the charge mode in a second cycle subsequent to the discharge mode; and providing, during the charge mode, an emulated signal to the voltage regulator, the emulated signal generated based on the current through the inductor in the discharge mode.
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