公开(公告)号：US20130010526A1

公开(公告)日：2013-01-10

申请号：US13618860

申请日：2012-09-14

Applicant: Durai Vishak Nirmal Ramaswamy ,  Kirk D. Prall

Inventor： Durai Vishak Nirmal Ramaswamy ,  Kirk D. Prall

IPC: G11C11/00 ,  H01L45/00

CPC classification number: H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147

Abstract: Some embodiments include a memory device and methods of forming the same. The memory device can include an electrode coupled to a memory element. The electrode can include different materials located at different portions of the electrode. The materials can create different dielectrics contacting the memory elements at different locations. Various states of the materials in the memory device can be used to represent stored information. Other embodiments are described.

Abstract translation: 一些实施例包括存储器件及其形成方法。 存储器件可以包括耦合到存储元件的电极。 电极可以包括位于电极的不同部分的不同材料。 这些材料可以在不同位置产生接触存储元件的不同电介质。 可以使用存储器件中的材料的各种状态来表示存储的信息。 描述其他实施例。

公开(公告)号：US07956402B2

公开(公告)日：2011-06-07

申请号：US11970843

申请日：2008-01-11

Applicant: Chun Chen ,  Kirk D. Prall

Inventor： Chun Chen ,  Kirk D. Prall

IPC: H01L29/788

CPC classification number: H01L29/42332 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7883

Abstract: The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method includes forming a first dielectric layer on a semiconductor substrate and forming a floating gate above the first dielectric layer, the floating gate comprised of a first layer doped with a first type of dopant material and a second layer doped with a second type of dopant material that is opposite the first type of dopant material in the first layer. The method further includes forming a second dielectric layer above the floating gate, forming a control gate above the second dielectric layer, and forming a source and a drain in the substrate.

Abstract translation: 本发明提供一种在半导体存储元件中形成双掺杂多晶硅浮动栅极的方法和装置。 该方法包括在半导体衬底上形成第一介电层并在第一介电层上形成浮置栅极，浮置栅极包括掺杂有第一类掺杂剂材料的第一层和掺杂有第二类掺杂剂的第二层 与第一层中的第一种掺杂剂材料相反的材料。 该方法还包括在浮置栅极上形成第二电介质层，在第二电介质层上形成控制栅极，以及在衬底中形成源极和漏极。

公开(公告)号：US07955935B2

公开(公告)日：2011-06-07

申请号：US11513933

申请日：2006-08-31

Applicant: Gurtej S. Sandhu ,  Kirk D. Prall

Inventor： Gurtej S. Sandhu ,  Kirk D. Prall

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L29/42332

Abstract: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the intergate dielectric layer and the nanodots can be removed with an etch selective to the intergate dielectric layer.

Abstract translation: 一种制造存储单元的方法，包括在第一介电层上形成纳米点并在纳米点上形成隔间电介质层，其中隔间电介质层封装在纳米点上。 为了形成存储器单元的侧壁，隔离介电层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。 在侧壁上形成间隔层以覆盖已经沉积纳米点的位置，并且可以用对栅极间电介质层选择性的蚀刻来去除间隔栅电介质层和纳米点的剩余部分。

公开(公告)号：US07881113B2

公开(公告)日：2011-02-01

申请号：US11703487

申请日：2007-02-07

Applicant: Lyle D. Jones ,  Roger W. Lindsay ,  Kirk D. Prall

Inventor： Lyle D. Jones ,  Roger W. Lindsay ,  Kirk D. Prall

IPC: G11C16/04

CPC classification number: H01L27/115 ,  G11C5/02 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11524

Abstract: A relaxed metal pitch architecture may include a bit line and a first active area string and a second active area string. The bit line may be directly coupled to the first active area string and to the second active area string. The relaxed metal pitch architecture may be applied to a non-volatile memory structure.

Abstract translation: 轻松的金属间距结构可以包括位线和第一有效区域串和第二有效区域串。 位线可以直接耦合到第一有效区域串和第二有效区域串。 轻松的金属间距结构可以应用于非易失性存储器结构。

公开(公告)号：US20100213458A1

公开(公告)日：2010-08-26

申请号：US12390703

申请日：2009-02-23

Applicant: Kirk D. Prall

Inventor： Kirk D. Prall

IPC: H01L29/12 ,  H01L21/34

CPC classification number: H01L27/12 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/8221 ,  H01L27/10873 ,  H01L27/11514 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11597 ,  H01L27/1225 ,  H01L29/66825 ,  H01L29/7869 ,  H01L29/7881

Abstract: Rigid semiconductor memory using amorphous metal oxide semiconductor channels are useful in the production of thin-film transistor memory devices. Such devices include single-layer and multi-layer memory arrays of volatile or non-volatile memory cells. The memory cells can be formed to have a gate stack overlying an amorphous metal oxide semiconductor, with amorphous metal oxide semiconductor channels.

Abstract translation: 使用非晶金属氧化物半导体通道的刚性半导体存储器可用于制造薄膜晶体管存储器件。 这样的设备包括易失性或非易失性存储单元的单层和多层存储器阵列。 存储单元可以形成为具有覆盖在非晶金属氧化物半导体上的栅极堆叠，具有无定形金属氧化物半导体沟道。

公开(公告)号：US20080128782A1

公开(公告)日：2008-06-05

申请号：US11970843

申请日：2008-01-11

Applicant: CHUN CHEN ,  KIRK D. PRALL

Inventor： CHUN CHEN ,  KIRK D. PRALL

IPC: H01L29/00

CPC classification number: H01L29/42332 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7883

Abstract: The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method includes forming a first dielectric layer on a semiconductor substrate and forming a floating gate above the first dielectric layer, the floating gate comprised of a first layer doped with a first type of dopant material and a second layer doped with a second type of dopant material that is opposite the first type of dopant material in the first layer. The method further includes forming a second dielectric layer above the floating gate, forming a control gate above the second dielectric layer, and forming a source and a drain in the substrate.

Abstract translation: 本发明提供一种在半导体存储元件中形成双掺杂多晶硅浮动栅极的方法和装置。 该方法包括在半导体衬底上形成第一介电层并在第一介电层上形成浮置栅极，浮置栅极包括掺杂有第一类掺杂剂材料的第一层和掺杂有第二类掺杂剂的第二层 与第一层中的第一种掺杂剂材料相反的材料。 该方法还包括在浮置栅极上形成第二电介质层，在第二电介质层上形成控制栅极，以及在衬底中形成源极和漏极。

公开(公告)号：US07301804B2

公开(公告)日：2007-11-27

申请号：US11346131

申请日：2006-02-02

Applicant: Kirk D. Prall ,  Leonard Forbes

Inventor： Kirk D. Prall ,  Leonard Forbes

IPC: H01L21/336 ,  G11C11/34

CPC classification number: H01L27/11568 ,  G11C11/5692 ,  G11C16/0475 ,  H01L27/115

Abstract: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

公开(公告)号：US07279740B2

公开(公告)日：2007-10-09

申请号：US11127618

申请日：2005-05-12

Applicant: Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

Inventor： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513

Abstract: Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory cells of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. A positive voltage erase process via hole tunneling is also provided.

Abstract translation: 描述了非易失性存储器件和阵列，其有助于在NOR或NAND存储器架构中的浮动栅极存储器单元中使用具有非对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和用电子和空穴擦除，同时保持 高电荷阻挡屏障和深载体捕获位点，具有良好的电荷保留性。 直接隧道编程和擦除功能可以减少高能量载体对栅极堆叠和晶格的损害，减少写入疲劳和泄漏问题，并增强器件寿命。 本发明的存储器单元还允许在单个存储器单元中进行多位存储，并允许以降低的电压进行编程和擦除。 还提供了正电压擦除处理通孔隧穿。

公开(公告)号：US07112815B2

公开(公告)日：2006-09-26

申请号：US10786765

申请日：2004-02-25

Applicant: Kirk D. Prall

Inventor： Kirk D. Prall

IPC: H01L47/00

CPC classification number: G11C16/04

Abstract: Multi-layer memory arrays and methods are provided. A memory array has two or more layers of memory material, each layer of memory material having an array of memory cells. A first contact penetrates through each layer of memory material in a first plane and is electrically connected to each layer of memory material so as to electrically interconnect the layers of memory material in the first plane. A second contact penetrates through at least one of the layers of memory material in a second plane substantially perpendicular to the first plane.

Abstract translation: 提供了多层存储器阵列和方法。 存储器阵列具有两层或多层存储器材料，每层存储器材料具有存储单元阵列。 第一接触件穿过第一平面中的每层存储器材料并且电连接到每层存储器材料，以便使第一平面中的存储材料层电互连。 第二接触件穿过基本上垂直于第一平面的第二平面中的记忆材料层中的至少一层。

公开(公告)号：US06858526B2

公开(公告)日：2005-02-22

申请号：US09820468

申请日：2001-03-28

Applicant: Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

Inventor： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

IPC: H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763 ,  H01L21/302

CPC classification number: H01L23/5222 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.

Abstract translation: 本发明包括在导电元件之间形成绝缘材料的方法。 在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。 另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。 在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。 在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。