公开(公告)号：US20080023733A1

公开(公告)日：2008-01-31

申请号：US11860362

申请日：2007-09-24

Applicant: Min-Hung LEE ,  Cheng-Yeh Yu ,  Shing-Chii Lu ,  Chee-Wee Liu

Inventor： Min-Hung LEE ,  Cheng-Yeh Yu ,  Shing-Chii Lu ,  Chee-Wee Liu

IPC: H01L29/78

CPC classification number: H01L21/26506 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/938

Abstract: Fabrication methods for compressive strained-silicon by ion implantation. Ions are implanted into a silicon-containing substrate and high temperature processing converts the vicinity of the ion-contained region into strained-silicon. Transistors fabricated by the method are also provided.

Abstract translation: 通过离子注入制备压应变硅的制备方法。 将离子注入到含硅衬底中，并且高温处理将离子包含区域的附近转变为应变硅。 还提供了通过该方法制造的晶体管。

公开(公告)号：US20060284164A1

公开(公告)日：2006-12-21

申请号：US11216179

申请日：2005-09-01

Applicant: Min-Hung Lee ,  Cheng-Yeh Yu ,  Chee-Wee Liu

Inventor： Min-Hung Lee ,  Cheng-Yeh Yu ,  Chee-Wee Liu

IPC: H01L31/00

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262

Abstract: A strained germanium field effect transistor (FET) and method of making the same, comprise forming a germanium layer on a substrate, then forming a Si protective layer on the germanium layer, next forming a gate insulation layer on the Si protective layer, and fmally positioning a gate on the gate insulation layer. The germanium layer is used as a carrier transport channel of the strained germanium FET to improve the drive current and the carrier mobility, and to increase the devices performance effectively. And because the Si protective layer is on the germanium layer, the interface property between the germanium layer and the gate insulation layer is improved.

Abstract translation: 应变锗场效应晶体管（FET）及其制造方法包括在衬底上形成锗层，然后在锗层上形成Si保护层，接着在Si保护层上形成栅极绝缘层，并且最终形成 在栅极绝缘层上定位栅极。 锗层用作应变锗FET的载流子传输通道，以提高驱动电流和载流子迁移率，并有效提高器件性能。 并且由于Si保护层在锗层上，所以锗层和栅极绝缘层之间的界面性能得到改善。

公开(公告)号：US20060263959A1

公开(公告)日：2006-11-23

申请号：US11228340

申请日：2005-09-19

Applicant: Cha-Hsin Lin ,  Zing-Way Pei ,  Chee-Wee Liu

Inventor： Cha-Hsin Lin ,  Zing-Way Pei ,  Chee-Wee Liu

IPC: H01L21/8234

CPC classification number: H01L21/823828 ,  H01L21/823807

Abstract: A method for fabricating a semiconductor device is provided. The method mainly involves steps of forming at least one first patterned high stress layer below a silicon substrate, then forming a semiconductor device onto the substrate, and forming at least one second patterned high stress layer on the semiconductor device. According to the method, the characteristics of the PMOS and the NMOS transistors formed on the same wafer may be improved simultaneously, by utilizing the stress of the patterned layers of high stress material. Further, the mobility of the carriers is enhanced, so that the output characteristic of the transistors can be improved.

Abstract translation: 提供一种制造半导体器件的方法。 该方法主要包括以下步骤：在硅衬底下方形成至少一个第一图案化的高应力层，然后在衬底上形成半导体器件，并在半导体器件上形成至少一个第二图案化的高应力层。 根据该方法，通过利用高应力材料的图案化层的应力，可以同时改善形成在同一晶片上的PMOS和NMOS晶体管的特性。 此外，载流子的迁移率增强，从而可以提高晶体管的输出特性。

公开(公告)号：US07102153B2

公开(公告)日：2006-09-05

申请号：US10919323

申请日：2004-08-17

Applicant: Pang-Shiu Chen ,  Sheng-Wei Lee ,  Lih-Juann Chen ,  Chee-Wee Liu

Inventor： Pang-Shiu Chen ,  Sheng-Wei Lee ,  Lih-Juann Chen ,  Chee-Wee Liu

IPC: H01L29/06

CPC classification number: B82Y30/00 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/02532

Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.

公开(公告)号：US06963089B2

公开(公告)日：2005-11-08

申请号：US10720117

申请日：2003-11-25

Applicant: Jin-Wei Shi ,  Chee-Wee Liu

Inventor： Jin-Wei Shi ,  Chee-Wee Liu

IPC: H01L31/08 ,  H01L31/107

CPC classification number: B82Y10/00 ,  H01L31/107

Abstract: An avalanche photo-detector (APD) is disclosed, which can reduce device capacitance, operating voltage, carrier transport time and dark current as well as increasing response speed and output power. Thus, an avalanche photo-detector (APD) with high saturation power, high gain-bandwidth product, low noise, fast response, low dark current is achieved. The APD includes an absorption layer with graded doping for converting an incident light into carriers, an undoped multiplication layer for multiplying current by means of receiving carriers, a doped field buffer layer sandwiched between the absorption layer and the multiplication layer for concentrating an electric field in the multiplication layer when a bias voltage is applied, and an undoped drift layer sandwiched between the absorption layer and the field buffer layer for capacitance reduction.

Abstract translation: 公开了一种雪崩光电检测器（APD），可以降低器件电容，工作电压，载流子传输时间和暗电流以及响应速度和输出功率。 因此，实现了具有高饱和功率，高增益带宽乘积，低噪声，快速响应，低暗电流的雪崩光电检测器（APD）。 APD包括具有用于将入射光转换成载流子的渐变掺杂的吸收层，用于通过接收载流子来乘以电流的未掺杂乘法层，夹在吸收层和乘法层之间的掺杂场缓冲层，用于将电场集中 施加偏置电压时的倍增层和夹在吸收层和场缓冲层之间的未掺杂漂移层用于电容降低。

公开(公告)号：US20050153491A1

公开(公告)日：2005-07-14

申请号：US10838252

申请日：2004-05-05

Applicant: Yang-Tai Tseng ,  Pang-Shiu Chen ,  Chee-Wee Liu

Inventor： Yang-Tai Tseng ,  Pang-Shiu Chen ,  Chee-Wee Liu

IPC: C30B1/02 ,  C30B29/52 ,  H01L21/20 ,  H01L21/265 ,  H01L29/10 ,  H01L21/00 ,  H01L21/84 ,  H01L21/76 ,  C30B1/00

CPC classification number: H01L21/26506 ,  C30B1/023 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02694 ,  H01L29/1054

Abstract: A process of forming a low-strain crystal layer having low cell dislocation, low surface roughness and low thickness comprises: forming at least one crystal layer on a substrate; patterning the crystal layer by exposure and development to form an ion-doping region; doping ions in the ion-doping region of the crystal layer to convert the crystal layer to an amorphous layer; performing a planarization process on the amorphous layer; and annealing the amorphous layer to convert the amorphous layer to a low-strain crystal layer.

Abstract translation: 形成具有低电池位错，低表面粗糙度和低厚度的低应变晶体层的工艺包括：在衬底上形成至少一个晶体层; 通过曝光和显影来图案化晶体层以形成离子掺杂区域; 在晶体层的离子掺杂区域掺杂离子以将晶体层转化为非晶层; 对非晶层进行平面化处理; 并且使非晶层退火以将非晶层转变成低应变晶体层。

公开(公告)号：US06916674B2

公开(公告)日：2005-07-12

申请号：US10704632

申请日：2003-11-12

Applicant: Pang-Shiu Chen ,  Buo-Chin Hsu ,  Chee-Wee Liu

Inventor： Pang-Shiu Chen ,  Buo-Chin Hsu ,  Chee-Wee Liu

IPC: H01L21/20 ,  H01L21/31 ,  H01L31/0352 ,  H01L33/00 ,  H01L21/00

CPC classification number: B82Y10/00 ,  B82Y20/00 ,  H01L21/02373 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/0259 ,  H01L31/0352

Abstract: The present invention discloses a method for fabricating multiple-thickness insulator layers via strain field generated by stress. The strain field is used for alternating a develop mechanism of insulator layers on the quantum dots. By forming the multiple-thickness insulator layers at various developing rates, not only leakage current is prevented, but also components are kept isolated in the nano-electronics components. In nano-electronics manufacturing, the method for fabricating multiple-thickness insulator layers results in both better product reliability and the yield rate. It is potential for integral circuit manufacturing.

Abstract translation: 本发明公开了一种通过应力产生的应变场来制造多层绝缘体层的方法。 应变场用于交替量子点上的绝缘体层的显影机制。 通过以各种显影速率形成多层绝缘体层，不仅可以防止泄漏电流，还可以在纳米电子部件中保持隔离。 在纳米电子制造中，制造多层绝缘体层的方法产生更好的产品可靠性和产率。 它是集成电路制造的潜力。

公开(公告)号：US20050082567A1

公开(公告)日：2005-04-21

申请号：US10847913

申请日：2004-05-19

Applicant: Peng Shiu Chen ,  Yang Tai Tseng ,  Chee Wee Liu

Inventor： Peng Shiu Chen ,  Yang Tai Tseng ,  Chee Wee Liu

IPC: H01L21/20 ,  H01L21/205 ,  H01L21/302 ,  H01L31/072

CPC classification number: H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532

Abstract: A structure of the relaxed SiGe epitaxial layer and a fabrication method comprises a Si substrate, a Si interfacial layer positioning on the substrate, a SiGe graded buffer layer positioning on the Si interfacial layer, and a uniform SiGe epitaxy layer positioning on the SiGe graded buffer layer. It uses a mesa structure and obtains a highly relaxed SiGe epitaxial layer with a low defect density of threading dislocations, a smooth surface. A strained Si can be formed on the strained relaxation layer. The strained Si, the strained Ge, the strained Si/Ge can apply to the high-speed planar electronic devices. By using a mesa structure, it can efficiently decrease the required growth time and cost in the conventional relaxed SiGe epitaxy layer.

Abstract translation: 松弛SiGe外延层的结构和制造方法包括Si衬底，在衬底上定位的Si界面层，定位在Si界面层上的SiGe分级缓冲层，以及定位在SiGe分级缓冲层上的均匀SiGe外延层 层。 它采用台面结构，并获得具有低缺陷密度的穿透位错，光滑表面的高度松弛的SiGe外延层。 可以在应变弛豫层上形成应变Si。 应变Si，应变Ge，应变Si / Ge可应用于高速平面电子器件。 通过使用台面结构，可以有效地减少传统的弛豫SiGe外延层所需的生长时间和成本。

公开(公告)号：US20050045870A1

公开(公告)日：2005-03-03

申请号：US10919323

申请日：2004-08-17

Applicant: Pang Chen ,  Sheng-Wei Lee ,  Lih-Juann Chen ,  Chee-Wee Liu

Inventor： Pang Chen ,  Sheng-Wei Lee ,  Lih-Juann Chen ,  Chee-Wee Liu

IPC: C30B1/00 ,  H01L21/20 ,  H01L21/36 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L33/00

CPC classification number: B82Y30/00 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/02532

Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.

Abstract translation: 公开了一种用于在衬底上生长具有多个Ge量子点（QD）的应变Si层和松弛SiGe层的方法。 该方法可以减少穿透位错密度，降低应变硅的表面粗糙度，并进一步缩短形成外延层的生长时间，而不是常规方法。 该方法包括以下步骤：提供硅衬底，形成多个Ge量子点层; 形成一层轻松的SixGe1-x; 并在亚序列中形成应变硅层; 其中x大于0且小于1。

公开(公告)号：US08009479B2

公开(公告)日：2011-08-30

申请号：US12617516

申请日：2009-11-12

Applicant: Yen-Ting Chen ,  Ching-Fang Huang ,  Hung-Chang Sun ,  Chee Wee Liu

Inventor： Yen-Ting Chen ,  Ching-Fang Huang ,  Hung-Chang Sun ,  Chee Wee Liu

IPC: G11C16/06

CPC classification number: G11C16/0408 ,  G11C16/02 ,  G11C2211/4016 ,  H01L29/66825 ,  H01L29/685 ,  H01L29/788

Abstract: A non-volatile memory is provided. The non-volatile memory comprises at least a silicon-on-insulator transistor including a substrate; an insulating layer disposed on the substrate; an active region disposed on the insulating layer; and an energy barrier device disposed in the active region and outputting a relatively small current when the non-volatile memory is read.

Abstract translation: 提供非易失性存储器。 非易失性存储器至少包括一个包括衬底的绝缘体上硅晶体管; 设置在所述基板上的绝缘层; 设置在绝缘层上的有源区; 以及设置在有源区域中并且在读取非易失性存储器时输出相对小的电流的能量屏障装置。