公开(公告)号：US20120133030A1

公开(公告)日：2012-05-31

申请号：US12969250

申请日：2010-12-15

Applicant: Chung-Chih Wang ,  Pei-Jer Tzeng ,  Cha-Hsin Lin ,  Tzu-Kun Ku

Inventor： Chung-Chih Wang ,  Pei-Jer Tzeng ,  Cha-Hsin Lin ,  Tzu-Kun Ku

IPC: H01L29/41

CPC classification number: H01L21/76898 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/562 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/13023 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/81 ,  H01L2224/8114 ,  H01L2224/81911 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

Abstract translation: 本公开提供TSV衬底结构和多个衬底结构的层叠组件，TSV衬底结构包括：衬底，其包括第一表面，相应的第二表面以及将第一表面与第二表面通过第二表面连通的TSV 基质; 以及完全填充TSV的导体单元，所述导体单元包括分别具有对应于所述基板的第一和第二表面的第一和第二端的导体本体。

公开(公告)号：US20100164062A1

公开(公告)日：2010-07-01

申请号：US12480694

申请日：2009-06-09

Applicant: Ching-Chiun Wang ,  Tai-Yuan Wu ,  Yu-Sheng Chen ,  Cha-Hsin Lin

Inventor： Ching-Chiun Wang ,  Tai-Yuan Wu ,  Yu-Sheng Chen ,  Cha-Hsin Lin

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/90 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L27/0629 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13157 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/013

Abstract: A method of manufacturing through-silicon-via (TSV) and a TSV structure are provided. The TSV structure includes a silicon substrate, an annular capacitor, a conductive through-via, a layer of low-k material, and a bump. The annular capacitor is within the silicon substrate and constituted of a first conductive layer, a capacitor dielectric layer, and a second conductive layer from the inside to the outside. The conductive through-via is disposed in the silicon substrate surrounded by the annular capacitor, and the layer of low-k material is between the annular capacitor and the conductive through-via. The bump is in touch with the conductive through-via for bonding other chip.

Abstract translation: 提供了通过硅通孔（TSV）和TSV结构的方法。 TSV结构包括硅衬底，环形电容器，导电通孔，低k材料层和凸块。 环形电容器在硅衬底内，由第一导电层，电容器电介质层和从内向外的第二导电层构成。 导电通孔设置在由环形电容器包围的硅衬底中，低k材料层位于环形电容器和导电通孔之间。 凸块与用于粘合其他芯片的导电通孔相接触。

公开(公告)号：US07700988B2

公开(公告)日：2010-04-20

申请号：US11386362

申请日：2006-03-21

Applicant: Cha-Hsin Lin ,  Ching-Chiun Wang ,  Lurng-Shehng Lee

Inventor： Cha-Hsin Lin ,  Ching-Chiun Wang ,  Lurng-Shehng Lee

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L28/56 ,  H01L21/02186 ,  H01L21/022 ,  H01L21/31604

Abstract: A metal-insulator-metal (MIM) capacitor having a top electrode, a bottom electrode and a capacitor dielectric layer is provided. The top electrode is located over the bottom electrode and the capacitor dielectric layer is disposed between the top and the bottom electrode. The capacitor dielectric layer comprises several titanium oxide (TiO2) layers and at least one tetragonal structure material layer. The tetragonal structure material layer is disposed between two titanium oxide layers and each tetragonal structure material layer has the same or a different thickness. Leakage path can be cut off through the tetragonal material layer between the titanium oxide layers. In the meantime, the tetragonal structure material layer can induce the titanium oxide layers to transform into a high k rutile phase.

Abstract translation: 提供了具有顶部电极，底部电极和电容器电介质层的金属 - 绝缘体金属（MIM）电容器。 顶部电极位于底部电极之上，并且电容器介电层设置在顶部和底部电极之间。 电容器介电层包括几个氧化钛（TiO 2）层和至少一个四方结构材料层。 四方结构材料层设置在两个氧化钛层之间，每个四边形结构材料层具有相同或不同的厚度。 可以通过钛氧化物层之间的四方材料层来切断泄漏路径。 同时，四方结构材料层可以诱导氧化钛层转变成高k金红石相。

公开(公告)号：US07589373B2

公开(公告)日：2009-09-15

申请号：US12353244

申请日：2009-01-13

Applicant: Cha-Hsin Lin ,  Lurng-Shehng Lee

Inventor： Cha-Hsin Lin ,  Lurng-Shehng Lee

IPC: H01L29/94

CPC classification number: H01L29/792 ,  H01L21/28282

Abstract: The present invention provides a semiconductor device, which includes a substrate and a sensing memory device. The substrate includes a metal-oxide-semiconductor transistor having a gate. The sensing memory device is disposed on the gate of the metal-oxide-semiconductor transistor and includes followings. The second conductive layer is covering the first conductive layer. The charge trapping layer is disposed between the first conductive layer and the second conductive layer, wherein the first conductive layer has a sensing region therein when charges stored in the charge trapping layer, and the sensing region is adjacent to the charge trapping layer. The first dielectric layer and the second dielectric layer are respectively disposed between the charge trapping layer and the first conductive layer and between the charge trapping layer and the second conductive layer, wherein a third dielectric layer is disposed between the gate and the sensing memory device.

Abstract translation: 本发明提供了一种半导体器件，其包括衬底和感测存储器件。 衬底包括具有栅极的金属氧化物半导体晶体管。 感测存储器件设置在金属氧化物半导体晶体管的栅极上并且包括以下。 第二导电层覆盖第一导电层。 电荷捕获层设置在第一导电层和第二导电层之间，其中当电荷存储在电荷俘获层中时，第一导电层中具有感测区域，并且感测区域与电荷俘获层相邻。 第一电介质层和第二电介质层分别设置在电荷俘获层和第一导电层之间以及电荷俘获层和第二导电层之间，其中第三介电层设置在栅极和感测存储器件之间。

公开(公告)号：US20090122465A1

公开(公告)日：2009-05-14

申请号：US12110363

申请日：2008-04-28

Applicant: Cha-Hsin Lin

Inventor： Cha-Hsin Lin

IPC: H01G9/025 ,  H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78681 ,  H01L51/0508 ,  H01L51/055

Abstract: Electrolyte transistor including a gate structure, two sources/drains, an electrolyte layer and a buried conductive layer is provided. The gate structure including a gate dielectric layer and a gate is located above a substrate. The two sources/drains are separated from each other and located above the substrate on each side the gate structure. The electrolyte layer is located between and contacts the two sources/drains, and located between and contacts the gate structure and the substrate. The buried conductive layer is located between the electrolyte layer and the substrate. The electrolyte layer between the two sources/drains includes a channel. The conductivity of the electrolyte layer between the two sources/drains is changed by a redox reaction, so as to turn on or turn off the channel.

Abstract translation: 提供包括栅极结构，两个源极/漏极，电解质层和掩埋导电层的电解质晶体管。 包括栅极电介质层和栅极的栅极结构位于衬底上方。 两个源极/漏极彼此分离并且位于栅极结构的每一侧上的衬底上方。 电解质层位于两个源极/漏极之间并且接触两个源极/漏极，并且位于栅极结构和衬底之间并且接触栅极结构和衬底。 掩埋导电层位于电解质层和基底之间。 两个源/排水沟之间的电解质层包括通道。 两个源极/漏极之间的电解质层的电导率通​​过氧化还原反应而变化，以便导通或关闭通道。

公开(公告)号：US20140008652A1

公开(公告)日：2014-01-09

申请号：US13589196

申请日：2012-08-20

Applicant: Tzu-Chien Hsu ,  Tzu-Kun Ku ,  Cha-Hsin Lin

Inventor： Tzu-Chien Hsu ,  Tzu-Kun Ku ,  Cha-Hsin Lin

IPC: H01L23/48 ,  H01L29/16

CPC classification number: H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through-substrate via structure including a substrate, a conductive layer, and a parasitic capacitance modulation layer is provided. The substrate has at least one opening. The opening is filled with the conductive layer. The parasitic capacitance modulation layer is disposed between the conductive layer and the substrate. The parasitic capacitance modulation layer is placed around the through-substrate via to reduce the depletion capacitance and further reduce the parasitic capacitance of the through-substrate via. Therefore, during transmission of signals with high frequency, the parasitic capacitance around the through-substrate via is rather small and thereby the operation speed of devices is increased.

Abstract translation: 提供了包括衬底，导电层和寄生电容调制层的贯通衬底通孔结构。 衬底具有至少一个开口。 开口填充有导电层。 寄生电容调制层设置在导电层和基板之间。 寄生电容调制层放置在贯通基板通孔周围，以减少耗尽电容，并进一步降低贯通基板通孔的寄生电容。 因此，在高频信号传输期间，贯通基板通孔周围的寄生电容相当小，从而提高了器件的工作速度。

公开(公告)号：US20130161825A1

公开(公告)日：2013-06-27

申请号：US13341846

申请日：2011-12-30

Applicant: TZU-CHIEN HSU ,  Tzu-Kun Ku ,  Cha-Hsin Lin

Inventor： TZU-CHIEN HSU ,  Tzu-Kun Ku ,  Cha-Hsin Lin

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/7682 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through substrate via (TSV) structure is provided, including: a substrate; an opening formed in a portion of the semiconductor substrate; a dielectric layer formed on the sidewall of the opening; a conductive pillar formed inside the opening; and at least a portion of the dielectric layer is removed to form void. Also provided is a method for fabricating a through substrate via (TSV) structure.

Abstract translation: 提供贯穿基板通孔（TSV）结构，包括：基板; 形成在所述半导体衬底的一部分中的开口; 形成在开口侧壁上的电介质层; 形成在开口内的导电柱; 并且去除介电层的至少一部分以形成空隙。 还提供了一种用于制造贯穿衬底通孔（TSV）结构的方法。

公开(公告)号：US20120322249A1

公开(公告)日：2012-12-20

申请号：US13596079

申请日：2012-08-28

Applicant: Jui-Chin Chen ,  Cha-Hsin Lin ,  John H. Lau ,  Tzu-Kun Ku

Inventor： Jui-Chin Chen ,  Cha-Hsin Lin ,  John H. Lau ,  Tzu-Kun Ku

IPC: H01L21/306

CPC classification number: H01L21/76898 ,  H01L21/02258 ,  H01L21/306 ,  H01L21/6835 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2225/06541 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: In a manufacturing method of a semiconductor structure, a substrate having a front surface and a back surface is provided. The front surface has a device layer thereon and conductive plugs electrically connected to the device layer. A thinning process is performed on the back surface of the substrate, such that the back surface of the substrate and surfaces of the conductive plugs have a distance therebetween. Holes are formed in the substrate from the back surface to the conductive plugs, so as to form a porous film. An oxidization process is performed, such that the porous film correspondingly is reacted to form an oxide material layer. A polishing process is performed on the oxide material layer to expose the surfaces of the conductive plugs.

Abstract translation: 在半导体结构体的制造方法中，设置具有正面和背面的基板。 前表面上有一个器件层，导电插头与器件层电连接。 在基板的背面进行薄化处理，使得基板的背面和导电塞的表面之间具有一定的距离。 在基板中从背面形成孔到导电塞，以便形成多孔膜。 进行氧化处理，使得多孔膜相应地反应以形成氧化物材料层。 在氧化物材料层上进行抛光处理以暴露导电塞的表面。

公开(公告)号：US08309402B2

公开(公告)日：2012-11-13

申请号：US13270199

申请日：2011-10-10

Applicant: Cha-Hsin Lin ,  Tzu-Kun Ku

Inventor： Cha-Hsin Lin ,  Tzu-Kun Ku

IPC: H01L21/00 ,  H01L23/12

CPC classification number: H01L23/147 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A manufacturing method of a semiconductor structure includes providing a substrate having an upper surface and a bottom surface. First openings are formed in the substrate. An oxidization process is performed to oxidize the substrate having the first openings therein to form an oxide-containing material layer, and the oxide-containing material layer has second openings therein. A conductive material is filled into the second openings to form conductive plugs. A first device layer is formed a first surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. A second device layer is formed on a second surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs.

Abstract translation: 半导体结构的制造方法包括提供具有上表面和底面的基板。 在基板上形成第一开口。 进行氧化处理以使其中具有第一开口的基板氧化以形成含氧化物的材料层，并且含氧化物的材料层在其中具有第二开口。 将导电材料填充到第二开口中以形成导电塞。 第一器件层形成为含氧化物材料层的第一表面，并且部分或全部电连接到导电插塞。 第二器件层形成在含氧化物材料层的第二表面上，并且部分或全部电连接到导电插塞。

公开(公告)号：US20120139105A1

公开(公告)日：2012-06-07

申请号：US13117172

申请日：2011-05-27

Applicant: Cha-Hsin Lin ,  Tzu-Kun Ku

Inventor： Cha-Hsin Lin ,  Tzu-Kun Ku

IPC: H01L23/498 ,  H01L21/28

CPC classification number: H01L23/147 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A manufacturing method of a semiconductor structure includes providing a substrate having an upper surface and a bottom surface. First openings are formed in the substrate. An oxidization process is performed to oxidize the substrate having the first openings therein to form an oxide-containing material layer, and the oxide-containing material layer has second openings therein. A conductive material is filled into the second openings to form conductive plugs. A first device layer is formed a first surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. A second device layer is formed on a second surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs.

Abstract translation: 半导体结构的制造方法包括提供具有上表面和底面的基板。 在基板上形成第一开口。 进行氧化处理以使其中具有第一开口的基板氧化以形成含氧化物的材料层，并且含氧化物的材料层在其中具有第二开口。 将导电材料填充到第二开口中以形成导电塞。 第一器件层形成为含氧化物材料层的第一表面，并且部分或全部电连接到导电插塞。 第二器件层形成在含氧化物材料层的第二表面上，并且部分或全部电连接到导电插塞。