公开(公告)号：US20080122483A1

公开(公告)日：2008-05-29

申请号：US11563632

申请日：2006-11-27

Applicant: Wilma Waiman Shiao ,  Stephen U. Yao ,  Ket-Chong Yap

Inventor： Wilma Waiman Shiao ,  Stephen U. Yao ,  Ket-Chong Yap

IPC: H03K19/173

CPC classification number: H03K19/0008 ,  H03K19/17736 ,  H03K19/17784

Abstract: An apparatus and method of reducing power consumption across a switch, such as an unprogrammed antifuse, is provided. The invention applies to antifuses, other switches such as transistor based switches, (e.g., FLASH, EEPROM and/or SRAM) and other devices exhibiting a leakage current, especially during a sleep or stand-by mode. During a sleep mode, such switches or other devices may be uncoupled from signals driving the switches, then terminals of each switch may be coupled to a common potential or allowed to float to a common potential thereby eliminating or reducing leakage currents through the switches.

Abstract translation: 提供了一种降低开关上的功耗的装置和方法，例如未编程的反熔丝。 本发明适用于反熔丝，诸如基于晶体管的开关的其它开关（例如，FLASH，EEPROM和/或SRAM）以及其它显示泄漏电流的器件，特别是在睡眠或待机模式期间。 在睡眠模式期间，这样的开关或其他装置可以与驱动开关的信号分离，然后每个开关的端子可以耦合到公共电位或允许浮动到公共电位，从而消除或减少通过开关的漏电流。

公开(公告)号：US6140837A

公开(公告)日：2000-10-31

申请号：US161192

申请日：1998-09-25

Applicant: David D. Eaton ,  Richard J. Wong ,  James M. Apland

Inventor： David D. Eaton ,  Richard J. Wong ,  James M. Apland

IPC: H01L21/8234 ,  H01L27/118 ,  H03K19/173 ,  G05F1/10 ,  H03K19/175

CPC classification number: H01L21/823462 ,  H01L27/11807

Abstract: A programmable device has digital logic elements and a programmable interconnect structure employing antifuses, the antifuses being programmable to connect selected ones of the digital logic elements together. During normal circuit operation, a first power input terminal is used to power the digital logic elements with a first supply voltage received on the first power input terminal. During normal circuit operation, a second power input terminal is used to protect circuitry of the programmable device from high voltage signals that may be driven onto terminals of the programmable device by circuitry external to the programmable device. During antifuse programming, the second power input terminal is used to drive charge pumps of programming drivers and/or programming control drivers. In some embodiments, the second power input terminal receives a voltage higher than the first supply voltage during antifuse programming such that the oscillating signal that drives the charge pumps has a larger amplitude thereby allowing back bias threshold voltages of transistors in the charge pumps to be overcome, facilitating starting of the charge pumps, and/or increasing charge pump efficiency.

Abstract translation: 可编程器件具有采用反熔丝的数字逻辑元件和可编程互连结构，反熔丝是可编程的，以将选定的数字逻辑元件连接在一起。 在正常电路操作期间，使用第一电力输入端子以在第一电力输入端子上接收的第一电源电压为数字逻辑元件供电。 在正常电路操作期间，使用第二电力输入端子来保护可编程器件的电路免受可编程器件外部的电路驱动到可编程器件的端子的高电压信号。 在反熔丝编程期间，第二电源输入端用于驱动编程驱动器和/或编程控制驱动器的电荷泵。 在一些实施例中，第二电力输入端子在反熔丝编程期间接收高于第一电源电压的电压，使得驱动电荷泵的振荡信号具有较大的幅度，从而允许克服电荷泵中晶体管的反向偏置阈值电压 ，促进电荷泵的启动和/或增加电荷泵效率。

公开(公告)号：US6130554A

公开(公告)日：2000-10-10

申请号：US932390

申请日：1997-09-17

Applicant: Paige A. Kolze ,  Andrew K. Chan ,  James A. Apland

Inventor： Paige A. Kolze ,  Andrew K. Chan ,  James A. Apland

IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: A programmable integrated circuit (see FIG. 13) includes a plurality of routing resources including collinearly extending routing wire segments and a test circuit for testing the integrity of the routing wire segments. The routing resource structures include a plurality of unprogrammed antifuses disposed between routing wire segments and a plurality of transistors disposed electrically in parallel with a corresponding respective one of the antifuses. The test circuit has a common node that may be coupled to a selected one of the routing resource structures for testing. In test mode, the test circuit detects whether a current flows through the selected routing resource structure and in response provides either a digital low value or a digital high value on an output node.

Abstract translation: 可编程集成电路（参见图13）包括多个路由资源，包括共线延伸的路由线段和用于测试路由线段完整性的测试电路。 路由资源结构包括布置在布线线段与多个晶体管之间的多个未编程的反熔丝，所述多个晶体管与相应的相应一个反熔丝电并联放置。 测试电路具有可以耦合到选择的一个路由资源结构以用于测试的公共节点。 在测试模式下，测试电路检测电流是否流过所选择的路由资源结构，并且响应于在输出节点上提供数字低值或数字高值。

公开(公告)号：US6097077A

公开(公告)日：2000-08-01

申请号：US75493

申请日：1998-05-08

Applicant: Kathryn E. Gordon ,  Richard J. Wong

Inventor： Kathryn E. Gordon ,  Richard J. Wong

IPC: H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract translation: 公开了具有抗熔丝的防潮和门阵列，其具有高的热稳定性，减小的尺寸，减小的漏电流，在未编程状态下的减小的电容，改善的制造产量和更可控的电特性。 一些反熔丝包括反熔丝通孔中的间隔物。 在一些反熔丝中，可编程材料是平面的，并且顶部或底部电极形成在反熔丝通孔中。 在一些栅极阵列中，反熔丝形成在介电分离两层布线通道之上，而不是在该介电层之下。

公开(公告)号：US6081129A

公开(公告)日：2000-06-27

申请号：US931893

申请日：1997-09-17

Applicant: James M. Apland ,  Paige A. Kolze

Inventor： James M. Apland ,  Paige A. Kolze

IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177 ,  H01L25/00

CPC classification number: H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: A programming architecture for a field programmable gate array (FPGA) employing antifuses is disclosed. To test the integrity of programming conductors, programming transistors, routing wire segments and a combinatorial portion of a logic module of the unprogrammed FPGA (see FIG. 16), a combination of digital logic values is supplied onto the inputs of the combinatorial portion in a test mode. A defect is determined to exist if the correct digital value is not then output by the combinatorial portion. The digital value output by the combinatorial portion is captured in the flip-flop of the logic module and is shifted out of the FPGA in a scan out test mode. A programming transistor, programming conductor and routing wire segment structure is also disclosed which facilitates such testing. In one embodiment (see FIG. 15), the gate of no programming transistor coupled to an output routing wire segment of the logic module (such as transistor 216) is permanently connected to the gate of any programming transistor coupled to an input routing wire segment of the logic module (such as transistors 200, 201 and 202).

Abstract translation: 公开了一种采用反熔丝的现场可编程门阵列（FPGA）的编程架构。 为了测试编程导体，编程晶体管，布线线段和未编程FPGA（参见图16）的逻辑模块的组合部分的完整性，数字逻辑值的组合被提供到组合部分的输入端 测试模式。 如果正确的数字值不由组合部分输出，则确定存在缺陷。 由组合部分输出的数字值被捕获在逻辑模块的触发器中，并以扫描输出测试模式从FPGA中移出。 还公开了编程晶体管，编程导体和布线线段结构，其有助于这种测试。 在一个实施例中（参见图15），耦合到逻辑模块（例如晶体管216）的输出布线线段的无编程晶体管的栅极永久连接到耦合到输入布线线段的任何编程晶体管的栅极 的逻辑模块（例如晶体管200,201和202）。

公开(公告)号：US6078191A

公开(公告)日：2000-06-20

申请号：US38728

申请日：1998-03-10

Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

IPC: H03K3/356 ,  H03K17/00 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1778 ,  H03K19/17792

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract translation: 现场可编程门阵列包括可编程路由网络，与可编程路由网络集成的可编程配置网络; 以及与可编程配置网络集成的逻辑单元。 逻辑单元包括四个双输入与门，两个六输入与门，三个多路复用器和延迟触发器。 逻辑单元是一种强大的通用逻辑构建块，适用于实现大多数TTL和门阵列宏图程序功能。 相当多种功能可以通过一个单元延迟来实现，包括宽达十三个输入的组合逻辑功能，最多三个输入的所有布尔传递函数，以及顺序触发器功能，如T，JK和带进位的计数。

公开(公告)号：US5989943A

公开(公告)日：1999-11-23

申请号：US447969

申请日：1989-12-08

Applicant: Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas ,  Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner

Inventor： Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas ,  Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner

IPC: H01L21/82 ,  H01L23/525 ,  H01L27/10 ,  H01L21/28

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

公开(公告)号：US5925920A

公开(公告)日：1999-07-20

申请号：US662056

申请日：1996-06-12

Applicant: James MacArthur ,  Timothy M. Lacey

Inventor： James MacArthur ,  Timothy M. Lacey

IPC: H03K19/177

CPC classification number: H03K19/17764 ,  H03K19/17736 ,  H03K19/1778

Abstract: The present invention provides a method and apparatus for high yield improvements in programmable logic devices using redundancy. The present invention concerns a programmable logic device comprising a plurality of routings lines coupled to a plurality of logic blocks when programmed. During programming, a path is routed through the routing lines by programming the selected programmable elements. The selected programmable elements are located at each interconnect point between at least two routing lines or two segments of a routing lines along the path. The programmable elements include at least two interconnect circuits coupled in parallel. The programmable element is successfully programmed when at least one of the interconnect circuits is functional after programming.

Abstract translation: 本发明提供一种使用冗余的可编程逻辑器件中高产率改进的方法和装置。 本发明涉及一种可编程逻辑器件，包括当被编程时耦合到多个逻辑块的多个路由线。 在编程期间，通过对所选择的可编程元件进行编程，路由路由路由。 所选择的可编程元件位于沿着路径的至少两个路由线路或路由线路的两个段之间的每个互连点处。 可编程元件包括并联耦合的至少两个互连电路。 当编程后至少一个互连电路起作用时，可编程元件被成功编程。

公开(公告)号：US5825201A

公开(公告)日：1998-10-20

申请号：US667702

申请日：1996-06-21

Applicant: Paige A. Kolze

Inventor： Paige A. Kolze

IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: A programming architecture for a field programmable gate array (FPGA) employing antifuses is disclosed. In one aspect, the number of programming conductors and the number of perpendicular programming control conductors for a logic module are substantially equal. In another aspect, programming current is supplied onto long routing wire segments via two programming transistors and two programming conductors. In another aspect, a pattern of programming drivers alternates from one side of the integrated circuit to the opposite side from one column of macrocells to the next. In other aspects, control conductors and programming conductors are tested with test antifuses and test transistors. In another aspect, adjacent logic modules have mirrored structures so that they can share an intervening programming conductor resource. In another aspect, L-shaped programming power busses are provided and in another aspect, an express wire is simultaneously driven with programming current from two different programming voltage terminals. In other aspects, a test circuit tests the integrity of collinear routing wire segments and output programming transistors are tested. In another aspect, antifuses on branches of clock conductors are programmed.

Abstract translation: 公开了一种采用反熔丝的现场可编程门阵列（FPGA）的编程架构。 在一个方面，逻辑模块的编程导体的数量和垂直编程控制导体的数量基本相等。 在另一方面，通过两个编程晶体管和两个编程导体将编程电流提供给长路由线段。 在另一方面，编程驱动器的模式从集成电路的一侧交替到从一列宏单元到另一列的相反侧。 在其他方面，使用测试反熔丝和测试晶体管测试控制导体和编程导体。 在另一方面，相邻逻辑模块具有镜像结构，使得它们可以共享中间编程导体资源。 在另一方面，提供L形编程功率总线，并且在另一方面，快速导线由来自两个不同编程电压端子的编程电流同时驱动。 在其他方面，测试电路测试共线路由线段的完整性，并对输出编程晶体管进行测试。 在另一方面，编程时钟导体的分支上的反熔丝。

公开(公告)号：US5825200A

公开(公告)日：1998-10-20

申请号：US929655

申请日：1997-09-17

Applicant: Paige A. Kolze

Inventor： Paige A. Kolze

IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: The programmable interconnect structure of a field programmable gate array (see FIG. 4B) includes a plurality of wire segments extending in a first direction, the wire segments being collinear with respect to each other. An antifuse is disposed between each pair of adjacent wire segments so that the adjacent wire segments can be coupled together. Programming conductors for supplying a programming voltage onto selected wire segments extend in a second direction perpendicular to the first direction. The programming drivers for driving some of the programming conductors are disposed on one side (for example above) of the wire segments whereas the programming drivers for driving others of the programming conductors are disposed on the opposite side (for example below) of the wire segments. The pattern for programming drivers coupled to programming conductors alternates from one side of the wire segments to the other from column to column across the field programmable gate array.

Abstract translation: 现场可编程门阵列（见图4B）的可编程互连结构包括沿第一方向延伸的多个线段，线段相对于彼此共线。 反熔丝设置在每对相邻的线段之间，使得相邻的线段可以耦合在一起。 用于将编程电压提供到所选择的线段上的编程导体沿垂直于第一方向的第二方向延伸。 用于驱动一些编程导体的编程驱动器设置在线段的一侧（例如上面），而用于驱动编程导体的其它编程导体的编程驱动器设置在线段的相对侧（例如下面） 。 耦合到编程导体的编程驱动器的模式从现场可编程门阵列的列到列的一侧交替到另一侧。