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公开(公告)号：US07646216B2
公开(公告)日：2010-01-12
申请号：US11563632
申请日：2006-11-27
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/0008 , H03K19/17736 , H03K19/17784
摘要： An apparatus and method of reducing power consumption across a switch, such as an unprogrammed antifuse, is provided. The invention applies to antifuses, other switches such as transistor based switches, (e.g., FLASH, EEPROM and/or SRAM) and other devices exhibiting a leakage current, especially during a sleep or stand-by mode. During a sleep mode, such switches or other devices may be uncoupled from signals driving the switches, then terminals of each switch may be coupled to a common potential or allowed to float to a common potential thereby eliminating or reducing leakage currents through the switches.
摘要翻译： 提供了一种降低开关上的功耗的装置和方法，例如未编程的反熔丝。 本发明适用于反熔丝，诸如基于晶体管的开关的其它开关（例如，FLASH，EEPROM和/或SRAM）以及其它显示泄漏电流的器件，特别是在睡眠或待机模式期间。 在睡眠模式期间，这样的开关或其他装置可以与驱动开关的信号分离，然后每个开关的端子可以耦合到公共电位或允许浮动到公共电位，从而消除或减少通过开关的漏电流。
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公开(公告)号：US20080122483A1
公开(公告)日：2008-05-29
申请号：US11563632
申请日：2006-11-27
IPC分类号： H03K19/173
CPC分类号： H03K19/0008 , H03K19/17736 , H03K19/17784
摘要： An apparatus and method of reducing power consumption across a switch, such as an unprogrammed antifuse, is provided. The invention applies to antifuses, other switches such as transistor based switches, (e.g., FLASH, EEPROM and/or SRAM) and other devices exhibiting a leakage current, especially during a sleep or stand-by mode. During a sleep mode, such switches or other devices may be uncoupled from signals driving the switches, then terminals of each switch may be coupled to a common potential or allowed to float to a common potential thereby eliminating or reducing leakage currents through the switches.
摘要翻译： 提供了一种降低开关上的功耗的装置和方法，例如未编程的反熔丝。 本发明适用于反熔丝，诸如基于晶体管的开关的其它开关（例如，FLASH，EEPROM和/或SRAM）以及其它显示泄漏电流的器件，特别是在睡眠或待机模式期间。 在睡眠模式期间，这样的开关或其他装置可以与驱动开关的信号分离，然后每个开关的端子可以耦合到公共电位或允许浮动到公共电位，从而消除或减少通过开关的漏电流。
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公开(公告)号：US20080133988A1
公开(公告)日：2008-06-05
申请号：US11565441
申请日：2006-11-30
IPC分类号： G01R31/28
CPC分类号： G01R31/318516
摘要： Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic.
摘要翻译： 通过可编程逻辑中的编程电路将输入和/或输出测试值路由输入和/或输出测试值作为信号从专用逻辑返回到专用逻辑，从而提供组合逻辑的测试。
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公开(公告)号：US08091001B2
公开(公告)日：2012-01-03
申请号：US11565441
申请日：2006-11-30
IPC分类号： G01R31/28
CPC分类号： G01R31/318516
摘要： Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic. Some embodiments of the present invention provide for a method for testing functional logic block of an application-specific standard product (ASSP) in a programmable logic device, the method comprising: storing an input value into a register; passing the input value from the register to combinatorial logic; producing an output value from the combinatorial logic; passing the output value from the combinatorial logic to the register; saving the output value in the register; and reading the output value out of the register.
摘要翻译： 通过可编程逻辑中的编程电路将输入和/或输出测试值路由输入和/或输出测试值作为信号从专用逻辑返回到专用逻辑，从而提供组合逻辑的测试。 本发明的一些实施例提供了一种用于在可编程逻辑设备中测试应用特定标准产品（ASSP）的功能逻辑块的方法，所述方法包括：将输入值存储到寄存器中; 将输入值从寄存器传递给组合逻辑; 从组合逻辑产生输出值; 将组合逻辑的输出值传递给寄存器; 将输出值保存在寄存器中; 并从寄存器读取输出值。
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公开(公告)号：US08261002B2
公开(公告)日：2012-09-04
申请号：US12198200
申请日：2008-08-26
申请人： Eric So , Stephen U. Yao , Alan Shiu Lung Tsun
发明人： Eric So , Stephen U. Yao , Alan Shiu Lung Tsun
CPC分类号： G06F13/4027
摘要： Embodiments of the present invention provide a unique capability of implementing a pair of pseudo-PHY interfaces using a bridge. From the host and device perspectives, the host and device communicate through a PHY interface. The bridge, however, avoids actually using a USB PHY interface. This PHY-less bridge allows communication between a host and a device at high speeds without high-power transceivers associated with a USB PHY interface. In accordance with the present invention, a host and a device may be coupled together using a PHY-less bridge using the same interface or translating between different interfaces by using a wrapper. Such PHY-less bridges include a UTMI-to-UTMI bridge, a UTMI-to-ULPI bridge, a ULPI-to-UTMI bridge and a ULPI-to-ULPI bridge, each avoiding the need for a USB PHY interface.
摘要翻译： 本发明的实施例提供了使用桥接器来实现一对伪PHY接口的独特能力。 从主机和设备的角度看，主机和设备通过PHY接口进行通信。 然而，桥接器避免了实际使用USB PHY接口。 该无PHY网桥允许主机和设备之间的高速通信，无需与USB PHY接口相关的高功率收发器。 根据本发明，主机和设备可以使用相同接口使用无PHY桥接器耦合在一起，或者通过使用包装器在不同接口之间进行转换。 这样的无PHY桥接器包括UTMI至UTMI桥，UTMI至ULPI桥，ULPI至UTMI桥和ULPI至ULPI桥，每个桥避免了对USB PHY接口的需要。
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公开(公告)号：US20090070515A1
公开(公告)日：2009-03-12
申请号：US12198200
申请日：2008-08-26
申请人： Eric So , Stephen U. Yao , Alan Shiu Lung Tsun
发明人： Eric So , Stephen U. Yao , Alan Shiu Lung Tsun
IPC分类号： G06F13/36
CPC分类号： G06F13/4027
摘要： Embodiments of the present invention provide a unique capability of implementing a pair of pseudo-PHY interfaces using a bridge. From the host and device perspectives, the host and device communicate through a PHY interface. The bridge, however, avoids actually using a USB PHY interface. This PHY-less bridge allows communication between a host and a device at high speeds without high-power transceivers associated with a USB PHY interface. In accordance with the present invention, a host and a device may be coupled together using a PHY-less bridge using the same interface or translating between different interfaces by using a wrapper. Such PHY-less bridges include a UTMI-to-UTMI bridge, a UTMI-to-ULPI bridge, a ULPI-to-UTMI bridge and a ULPI-to-ULPI bridge, each avoiding the need for a USB PHY interface.
摘要翻译： 本发明的实施例提供了使用桥接器来实现一对伪PHY接口的独特能力。 从主机和设备的角度看，主机和设备通过PHY接口进行通信。 然而，桥接器避免了实际使用USB PHY接口。 该无PHY网桥允许主机和设备之间的高速通信，无需与USB PHY接口相关的高功率收发器。 根据本发明，主机和设备可以使用相同接口使用无PHY桥接器耦合在一起，或者通过使用包装器在不同接口之间进行转换。 这样的无PHY桥接器包括UTMI至UTMI桥，UTMI至ULPI桥，ULPI至UTMI桥和ULPI至ULPI桥，每个桥避免了对USB PHY接口的需要。
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公开(公告)号：US07443222B1
公开(公告)日：2008-10-28
申请号：US11753531
申请日：2007-05-24
申请人： Timothy Saxe , Senani Gunaratna , Stephen U. Yao
发明人： Timothy Saxe , Senani Gunaratna , Stephen U. Yao
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： An implementation of an apparatus and method to generate a dynamically controlled clock is provided. The resulting clock reduces otherwise produced narrow clock pulses and allows for control from two separate control signals. A first control signal indicates a low power mode, for example a chip-wide low power mode. A second control signal indicates a user-selected mode to shutdown a selected clock.
摘要翻译： 提供了一种用于生成动态控制时钟的装置和方法的实现。 所产生的时钟减少了另外产生的窄时钟脉冲，并允许从两个单独的控制信号进行控制。 第一控制信号表示低功率模式，例如芯片级的低功率模式。 第二控制信号指示用户选择的关闭所选时钟的模式。
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