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公开(公告)号：US07646216B2
公开(公告)日：2010-01-12
申请号：US11563632
申请日：2006-11-27
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/0008 , H03K19/17736 , H03K19/17784
摘要： An apparatus and method of reducing power consumption across a switch, such as an unprogrammed antifuse, is provided. The invention applies to antifuses, other switches such as transistor based switches, (e.g., FLASH, EEPROM and/or SRAM) and other devices exhibiting a leakage current, especially during a sleep or stand-by mode. During a sleep mode, such switches or other devices may be uncoupled from signals driving the switches, then terminals of each switch may be coupled to a common potential or allowed to float to a common potential thereby eliminating or reducing leakage currents through the switches.
摘要翻译： 提供了一种降低开关上的功耗的装置和方法，例如未编程的反熔丝。 本发明适用于反熔丝，诸如基于晶体管的开关的其它开关（例如，FLASH，EEPROM和/或SRAM）以及其它显示泄漏电流的器件，特别是在睡眠或待机模式期间。 在睡眠模式期间，这样的开关或其他装置可以与驱动开关的信号分离，然后每个开关的端子可以耦合到公共电位或允许浮动到公共电位，从而消除或减少通过开关的漏电流。
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公开(公告)号：US20080122483A1
公开(公告)日：2008-05-29
申请号：US11563632
申请日：2006-11-27
IPC分类号： H03K19/173
CPC分类号： H03K19/0008 , H03K19/17736 , H03K19/17784
摘要： An apparatus and method of reducing power consumption across a switch, such as an unprogrammed antifuse, is provided. The invention applies to antifuses, other switches such as transistor based switches, (e.g., FLASH, EEPROM and/or SRAM) and other devices exhibiting a leakage current, especially during a sleep or stand-by mode. During a sleep mode, such switches or other devices may be uncoupled from signals driving the switches, then terminals of each switch may be coupled to a common potential or allowed to float to a common potential thereby eliminating or reducing leakage currents through the switches.
摘要翻译： 提供了一种降低开关上的功耗的装置和方法，例如未编程的反熔丝。 本发明适用于反熔丝，诸如基于晶体管的开关的其它开关（例如，FLASH，EEPROM和/或SRAM）以及其它显示泄漏电流的器件，特别是在睡眠或待机模式期间。 在睡眠模式期间，这样的开关或其他装置可以与驱动开关的信号分离，然后每个开关的端子可以耦合到公共电位或允许浮动到公共电位，从而消除或减少通过开关的漏电流。
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3.发明申请Adjustable interface buffer circuit between a programmable logic device and a dedicated device 有权可编程逻辑器件与专用器件之间的可调接口缓冲电路公开(公告)号：US20080074141A1
公开(公告)日：2008-03-27
申请号：US11525275
申请日：2006-09-21
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.
摘要翻译： 集成电路包括可编程逻辑器件，专用器件和两者之间的接口电路。 可以容易地修改接口电路以适应可嵌入到集成电路中的各种专用设备的不同接口I / O需求。 在一个实施例中，接口电路可以使用多个掩码可编程单向接口缓冲电路来实现。 可以通过在集成电路的单个金属层中的接口缓冲电路中重新布线导体，基于期望的专用器件的需要来反转任何所需数量的接口缓冲电路的方向。 在另一个实施例中，接口电路可以使用硬件可配置的双向接口缓冲电路来实现。
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4.发明申请Adjustable Interface Buffer Circuit Between A Programmable Logic Device And A Dedicated Device 有权可编程逻辑器件与专用器件之间的可调节接口缓冲电路公开(公告)号：US20110298492A1
公开(公告)日：2011-12-08
申请号：US13212522
申请日：2011-08-18
IPC分类号： H03K19/177 , H01L21/82
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.
摘要翻译： 集成电路包括可编程逻辑器件，专用器件和两者之间的接口电路。 可以容易地修改接口电路以适应可嵌入到集成电路中的各种专用设备的不同接口I / O需求。 在一个实施例中，接口电路可以使用多个掩码可编程单向接口缓冲电路来实现。 可以通过在集成电路的单个金属层中的接口缓冲电路中重新布线导体，基于期望的专用器件的需要来反转任何所需数量的接口缓冲电路的方向。 在另一个实施例中，接口电路可以使用硬件可配置的双向接口缓冲电路来实现。
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5.发明授权Adjustable interface buffer circuit between a programmable logic device and a dedicated device 有权可编程逻辑器件与专用器件之间的可调接口缓冲电路公开(公告)号：US08018248B2
公开(公告)日：2011-09-13
申请号：US11525275
申请日：2006-09-21
IPC分类号： H03K19/173
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.
摘要翻译： 集成电路包括可编程逻辑器件，专用器件和两者之间的接口电路。 可以容易地修改接口电路以适应可嵌入到集成电路中的各种专用设备的不同接口I / O需求。 在一个实施例中，接口电路可以使用多个掩码可编程单向接口缓冲电路来实现。 可以通过在集成电路的单个金属层中的接口缓冲电路中重新布线导体，基于期望的专用器件的需要来反转任何所需数量的接口缓冲电路的方向。 在另一个实施例中，接口电路可以使用硬件可配置的双向接口缓冲电路来实现。
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6.发明授权Adjustable interface buffer circuit between a programmable logic device and a dedicated device 有权可编程逻辑器件与专用器件之间的可调接口缓冲电路公开(公告)号：US08487652B2
公开(公告)日：2013-07-16
申请号：US13212522
申请日：2011-08-18
IPC分类号： H03K19/173
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.
摘要翻译： 集成电路包括可编程逻辑器件，专用器件和两者之间的接口电路。 可以容易地修改接口电路以适应可嵌入到集成电路中的各种专用设备的不同接口I / O需求。 在一个实施例中，接口电路可以使用多个掩码可编程单向接口缓冲电路来实现。 可以通过在集成电路的单个金属层中的接口缓冲电路中重新布线导体，基于期望的专用器件的需要来反转任何所需数量的接口缓冲电路的方向。 在另一个实施例中，接口电路可以使用硬件可配置的双向接口缓冲电路来实现。
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公开(公告)号：US20080133988A1
公开(公告)日：2008-06-05
申请号：US11565441
申请日：2006-11-30
IPC分类号： G01R31/28
CPC分类号： G01R31/318516
摘要： Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic.
摘要翻译： 通过可编程逻辑中的编程电路将输入和/或输出测试值路由输入和/或输出测试值作为信号从专用逻辑返回到专用逻辑，从而提供组合逻辑的测试。
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公开(公告)号：US08091001B2
公开(公告)日：2012-01-03
申请号：US11565441
申请日：2006-11-30
IPC分类号： G01R31/28
CPC分类号： G01R31/318516
摘要： Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic. Some embodiments of the present invention provide for a method for testing functional logic block of an application-specific standard product (ASSP) in a programmable logic device, the method comprising: storing an input value into a register; passing the input value from the register to combinatorial logic; producing an output value from the combinatorial logic; passing the output value from the combinatorial logic to the register; saving the output value in the register; and reading the output value out of the register.
摘要翻译： 通过可编程逻辑中的编程电路将输入和/或输出测试值路由输入和/或输出测试值作为信号从专用逻辑返回到专用逻辑，从而提供组合逻辑的测试。 本发明的一些实施例提供了一种用于在可编程逻辑设备中测试应用特定标准产品（ASSP）的功能逻辑块的方法，所述方法包括：将输入值存储到寄存器中; 将输入值从寄存器传递给组合逻辑; 从组合逻辑产生输出值; 将组合逻辑的输出值传递给寄存器; 将输出值保存在寄存器中; 并从寄存器读取输出值。
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公开(公告)号：US06542096B2
公开(公告)日：2003-04-01
申请号：US09939533
申请日：2001-08-24
IPC分类号： H03M900
CPC分类号： G11C7/222 , G11C7/1006 , G11C7/22 , H04J3/0685 , H04L7/0008 , H04L7/0083 , H04L7/033 , H04L7/10
摘要： In accordance with the invention, a serializer/deserializer core of a field programmable gate array includes a channel clock and a data channel. The data channel can serialize and deserialize data in two modes. In the first mode, an embedded clock signal is recovered from the data. In the second mode, a clock signal is provided by the channel clock. A selection signal determines in which mode each of the data channels in the serializer/deserializer core operates. An stair-step clock generator generates a series of rising edge signals used to serialize and deserialize data. The number of bits serialized and deserialized is determined by the control signals to a set of multiplexers in the stair-step clock generator which determine how many registers in the stair-step clock generator are activated.
摘要翻译： 根据本发明，现场可编程门阵列的串行器/解串器核心包括通道时钟和数据通道。 数据通道可以在两种模式下对数据进行序列化和反序列化。 在第一模式中，从数据中恢复嵌入的时钟信号。 在第二模式中，时钟信号由通道时钟提供。 选择信号确定串行器/解串器核心中的每个数据信道在哪种模式下操作。 阶梯式时钟发生器产生一系列用于串行化和反序列化数据的上升沿信号。 串行化和反序列化的位数由控制信号确定到楼梯级时钟发生器中的一组多路复用器，确定楼梯级时钟发生器中有多少个寄存器被激活。
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10.发明授权公开(公告)号：US06552410B1
公开(公告)日：2003-04-22
申请号：US09650773
申请日：2000-08-29
申请人： David D. Eaton , Ket-Chong Yap , Kevin K. Yee , E. Thomas Hart , Andrew K. Chan , Neal A. Palmer , Michael W. Dini , James Apland , Panawalge S. N. Gunaratna
发明人： David D. Eaton , Ket-Chong Yap , Kevin K. Yee , E. Thomas Hart , Andrew K. Chan , Neal A. Palmer , Michael W. Dini , James Apland , Panawalge S. N. Gunaratna
IPC分类号： H01L2200
CPC分类号： H03K19/1776 , H03K19/17732 , H03K19/17744
摘要： A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicates with the dedicated device is also located on the integrated circuit. The platform for the programmable circuit is one half of an existing programmable circuit, which eliminates the need to engineer the programmable circuit. The programmable circuit includes a clock network that receives clock signals from clock terminals as well as from a clock network in the dedicated device. The interface between the dedicated device and programmable circuit includes a number of conductors with buffers with testing circuitry. The testing circuitry includes a PMOS test transistor and a NMOS test transistor which permits testing of the buffers without programming the antifuses coupled to the conductors. The input/output terminals around the periphery and in the interface between the programmable circuit and dedicated device are tested using JTAG registers. The path of the test signal through the JTAG registers is selectable to pass around the periphery of both the programmable and dedicated devices or through the interface and around the periphery of only one of the programmable and dedicated devices.
摘要翻译： 诸如现场可编程门阵列的可编程电路以及诸如ASIC类型器件的专用器件在单个集成电路上与基于反熔丝的接口耦合在一起。 与专用设备通信的可配置非易失性存储器也位于集成电路上。 可编程电路的平台是现有可编程电路的一半，无需设计可编程电路。 可编程电路包括时钟网络，其从时钟端子以及专用器件中的时钟网络接收时钟信号。 专用器件和可编程电路之间的接口包括具有带测试电路的缓冲器的多个导体。 测试电路包括PMOS测试晶体管和NMOS测试晶体管，其允许对缓冲器进行测试而不编程耦合到导体的反熔丝。 使用JTAG寄存器测试周边和可编程电路与专用设备之间的接口中的输入/输出端子。 通过JTAG寄存器的测试信号的路径可选择通过可编程和专用设备的周边，或通过接口和仅可编程和专用设备之一的外围环绕。
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