公开(公告)号：US6148390A

公开(公告)日：2000-11-14

申请号：US662054

申请日：1996-06-12

Applicant: James MacArthur ,  Timothy M. Lacey

Inventor： James MacArthur ,  Timothy M. Lacey

IPC: G06F11/20 ,  G06F1/26

CPC classification number: H03K19/17764 ,  H03K19/17728 ,  H03K19/17736

Abstract: A programmable logic device having redundant sets of logic blocks which are capable of being enabled or disabled. The programmable logic device includes a plurality of sets of logic blocks, a plurality of routing resources and a programming circuit. Good logic blocks are enabled and fully operational when programmed. Nonfunctional logic blocks are disabled, powered off and invisible to the programming software. Each set of logic blocks has a corresponding routing resource. The routing resource corresponding to an enabled set of logic blocks is capable of being configured to provide input and output data paths for the enabled set of logic blocks. The routing resource corresponding to a disabled set of logic blocks is capable of being configured to bypass the disabled set of the logic blocks. The programming circuit stores the configuration data for the routing resources and is capable of providing the configuration data to a routing resource that corresponds to an enabled set of logic blocks.

公开(公告)号：US5925920A

公开(公告)日：1999-07-20

申请号：US662056

申请日：1996-06-12

Applicant: James MacArthur ,  Timothy M. Lacey

Inventor： James MacArthur ,  Timothy M. Lacey

IPC: H03K19/177

CPC classification number: H03K19/17764 ,  H03K19/17736 ,  H03K19/1778

Abstract: The present invention provides a method and apparatus for high yield improvements in programmable logic devices using redundancy. The present invention concerns a programmable logic device comprising a plurality of routings lines coupled to a plurality of logic blocks when programmed. During programming, a path is routed through the routing lines by programming the selected programmable elements. The selected programmable elements are located at each interconnect point between at least two routing lines or two segments of a routing lines along the path. The programmable elements include at least two interconnect circuits coupled in parallel. The programmable element is successfully programmed when at least one of the interconnect circuits is functional after programming.

Abstract translation: 本发明提供一种使用冗余的可编程逻辑器件中高产率改进的方法和装置。 本发明涉及一种可编程逻辑器件，包括当被编程时耦合到多个逻辑块的多个路由线。 在编程期间，通过对所选择的可编程元件进行编程，路由路由路由。 所选择的可编程元件位于沿着路径的至少两个路由线路或路由线路的两个段之间的每个互连点处。 可编程元件包括并联耦合的至少两个互连电路。 当编程后至少一个互连电路起作用时，可编程元件被成功编程。

公开(公告)号：US06563437B1

公开(公告)日：2003-05-13

申请号：US09677255

申请日：2000-10-02

Applicant: Greg J. Landry ,  Timothy M. Lacey

Inventor： Greg J. Landry ,  Timothy M. Lacey

IPC: H03M734

CPC classification number: G06F17/5054

Abstract: According to one embodiment, a method for programming a programmable logic device (PLD) may include reading configuration data from a memory device to program a first portion of a PLD to function as a data decompression circuit (304, 308). Compressed configuration data may then be read and decompressed by the first portion and used to program a second portion (310, 312, 315) with a user determined function. A first portion may then be reprogrammed with a user determined function (320, 324).

Abstract translation: 根据一个实施例，一种用于编程可编程逻辑器件（PLD）的方法可以包括从存储器件读取配置数据以编程PLD的第一部分以用作数据解压缩电路（304,308）。 然后可以由第一部分读取和解压缩压缩的配置数据，并且用于以用户确定的功能对第二部分（310,312,315）进行编程。 然后可以用用户确定的功能重新编程第一部分（320,324）。

公开(公告)号：US6130842A

公开(公告)日：2000-10-10

申请号：US908861

申请日：1997-08-08

Applicant: Timothy M. Lacey ,  Khaldoon Abugharbieh

Inventor： Timothy M. Lacey ,  Khaldoon Abugharbieh

IPC: G11C29/50 ,  H03K19/177 ,  G11C29/00

CPC classification number: G11C29/028 ,  G11C29/50 ,  H03K19/1776 ,  H03K19/1778 ,  G11C16/04 ,  G11C2029/5004

Abstract: A voltage source is configured to produce a desired voltage and the desired voltage is applied to a programmable cell coupled to the voltage source. Configuration may be accomplished by loading a register with a programmed voltage value which may be received as a serial data stream through a test access port coupled to the register. For one embodiment, the voltage source may be coupled to a gate of the programmable cell, thus allowing testing of margin voltages of the programmable cell. In a further embodiment, the voltage source may be coupled to a drain of the programmable cell through a load line circuit, thus providing a programmed voltage for the programmable cell. In general then, the programmable voltage source is configurable to provide a voltage to the programmable cell in accordance with a programmed voltage value loaded into the programmable voltage source. The present invention may be embodied in a programmable device such as a PLD a CPLD or an FPGA and provides easily adjustable verify and/or program voltages, configurable through use of the programmable register, to test the operation of the programmable cell. The higher the bit count of the register, the more precise a verify and/or program voltage that may be provided.

Abstract translation: 电压源被配置为产生期望的电压，并且将期望的电压施加到耦合到电压源的可编程单元。 可以通过加载具有编程电压值的寄存器来实现配置，所述编程电压值可以通过耦合到寄存器的测试访问端口作为串行数据流来接收。 对于一个实施例，电压源可以耦合到可编程单元的栅极，从而允许测试可编程单元的裕度电压。 在另一实施例中，电压源可以通过负载线路电路耦合到可编程单元的漏极，从而为可编程单元提供编程电压。 通常，可编程电压源可配置为根据加载到可编程电压源中的编程电压值向可编程单元提供电压。 本发明可以体现在诸如PLD或CPLD的可编程器件中，并且通过使用可编程寄存器提供可配置的易于调整的校验和/或编程电压来测试可编程单元的操作。 寄存器的位计数越高，可能提供的验证和/或编程电压越精确。

公开(公告)号：US5831926A

公开(公告)日：1998-11-03

申请号：US473076

申请日：1995-06-07

Applicant: Christopher S. Norris ,  Timothy M. Lacey

Inventor： Christopher S. Norris ,  Timothy M. Lacey

IPC: G11C7/10 ,  G11C8/04 ,  G11C8/00

CPC classification number: G11C8/04 ,  G11C7/1018 ,  G11C7/1042

Abstract: The burst mode memory architecture using interleaved memory arrays provides even and odd EPROM arrays with data having even addresses stored in the even array and data having odd addresses stored in the odd array. A control circuit receives an initial address from a memory system controller and then accesses all data from the even and odd arrays within a burst address space containing the initial address. A pair of out-of-phase counters generate even and odd addresses, respectively, for accessing the even and odd arrays. Each counter increments addresses sequentially until a burst address space boundary is reached, then the counters wrap around to a beginning of a burst address space to generate any remaining addresses within a burst address space. The burst mode control circuitry is capable of processing a variety of burst sequencing modes. The burst address space size and the burst sequencing mode are selectable. A particular embodiment for generating an aligned sequential burst address sequence is described.

公开(公告)号：US5787047A

公开(公告)日：1998-07-28

申请号：US745876

申请日：1996-11-08

Applicant: Christopher S. Norris ,  Timothy M. Lacey

Inventor： Christopher S. Norris ,  Timothy M. Lacey

IPC: G11C7/10 ,  G11C8/04 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C8/04 ,  G11C7/1018 ,  G11C7/1042

Abstract: The burst mode memory architecture using interleaved memory arrays provides even and odd EPROM arrays with data having even addresses stored in the even array and data having odd addresses stored in the odd array. A control circuit receives an initial address from a memory system controller and then accesses all data from the even and odd arrays within a burst address space containing the initial address. A pair of out-of-phase counters generate even and odd addresses, respectively, for accessing the even and odd arrays. Each counter increments addresses sequentially until a burst address space boundary is reached, then the counters wrap around to a beginning of a burst address space to generate any remaining addresses within a burst address space. The burst mode control circuitry is capable of processing a variety of burst sequencing modes. The burst address space size and the burst sequencing mode are selectable. A particular embodiment for generating an aligned sequential burst address sequence is described.

公开(公告)号：US06512395B1

公开(公告)日：2003-01-28

申请号：US10024093

申请日：2001-12-18

Applicant: Timothy M. Lacey ,  David L. Johnson

Inventor： Timothy M. Lacey ,  David L. Johnson

IPC: H03K19177

CPC classification number: H03K19/1776

Abstract: An apparatus comprising a memory device and a programmable logic device. The memory device may be configured to (i) connect to a first bus and a second bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate the control signals.

公开(公告)号：US06373231B1

公开(公告)日：2002-04-16

申请号：US09730315

申请日：2000-12-05

Applicant: Timothy M. Lacey ,  Satish Saripella

Inventor： Timothy M. Lacey ,  Satish Saripella

IPC: G05F140

CPC classification number: G05F1/565

Abstract: A voltage regulator includes a static regulator that provides a static regulated supply output as a reference input to a dynamic regulator to provide a regulated supply voltage. In one embodiment, multiple dynamic regulators are connected to the static regulated supply output of the static regulator. The one or more dynamic regulators dynamically detect when the regulated supply voltage is loaded below a predetermined reference level, and provide extra current in response to prevent the regulated supply voltage from drooping. Since the static regulator is capable of handling large average currents, the dynamic regulator circuit can be smaller than a typical dynamic regulator for an equivalent load. Furthermore, since the dynamic regulator provides transient current requirements, the size of the static regulator may be likewise smaller in size than a typical static regulator for an equivalent load.

Abstract translation: 电压调节器包括静态调节器，其提供静态调节电源输出作为动态调节器的参考输入，以提供稳定的电源电压。 在一个实施例中，多个动态稳压器连接到静态调节器的静态稳压电源输出。 一个或多个动态调节器动态地检测何时将调节的电源电压加载到预定的参考电平以下，并响应于防止调节的电源电压下降而提供额外的电流。 由于静态调节器能够处理大的平均电流，因此动态调节器电路可以小于用于等效负载的典型动态调节器。 此外，由于动态调节器提供瞬态电流要求，所以静态调节器的尺寸可以与用于等效负载的典型静态调节器相比尺寸更小。

公开(公告)号：US5656949A

公开(公告)日：1997-08-12

申请号：US581064

申请日：1995-12-29

Applicant: Aaron S. Yip ,  Timothy M. Lacey ,  Anup K. Nayak ,  Rajiv Nema ,  Han-Kim Nguyen

Inventor： Aaron S. Yip ,  Timothy M. Lacey ,  Anup K. Nayak ,  Rajiv Nema ,  Han-Kim Nguyen

IPC: H03K19/177

CPC classification number: H03K19/177 ,  H03K19/17704

Abstract: A programmable circuit apparatus having a programmable circuit and an input/output circuit with a first terminal is provided. The programmable circuit apparatus includes a programming circuit, with a bus junction, for programming the programmable circuit. The programmable circuit apparatus further includes an isolation circuit having an isolation input, coupled to the first terminal, and an isolation output, coupled to the bus junction of the programming circuit. The isolation circuit further has an isolation control gate which can receive a control signal and in response to that signal, the control gate controllably couples the isolation input to the isolation output. The programmable circuit apparatus also includes an apparatus for testing the routing, the programming circuitry, and the programmable circuit with a minimal impact on the performance of the programmable circuit. The programmable circuit apparatus also has the ability to program three or more antifuses or other programmable elements simultaneously.

Abstract translation: 提供具有可编程电路和具有第一端子的输入/输出电路的可编程电路装置。 可编程电路装置包括具有用于编程可编程电路的总线结的编程电路。 可编程电路装置还包括隔离电路，该隔离电路具有耦合到第一端子的隔离输入端和耦合到编程电路总线结的隔离输出端。 隔离电路还具有可接收控制信号的隔离控制栅极，并且响应于该信号，控制栅极可控制地将隔离输入耦合到隔离输出端。 可编程电路装置还包括用于测试路由，编程电路和可编程电路的装置，对可编程电路的性能影响最小。 可编程电路装置还具有同时编程三个或多个反熔丝或其它可编程元件的能力。

公开(公告)号：US5638322A

公开(公告)日：1997-06-10

申请号：US503988

申请日：1995-07-19

Applicant: Timothy M. Lacey

Inventor： Timothy M. Lacey

IPC: G11C7/06 ,  G11C16/28 ,  G11C11/34

CPC classification number: G11C16/28 ,  G11C7/062

Abstract: A pseudo-differential sense amplifier with improved common mode noise rejection is disclosed. The sense amplifier is connected to a memory cell via an array path and generates an output signal indicative of the state of the memory cell. The sense amplifier includes an array load device connected via an array node to the array path, a reference load device connected via a reference node to a reference path, a differential stage having a first input connected to the reference node, a second input connected to the array node and an output generating the output signal. The sense amplifier further includes a balancing device, connected to the reference node, for compensating a change in signal, caused by a noise event, at the array node and, thus reducing a delay in the response of the sense amplifier when a transition in the state of the cell occurs.

Abstract translation: 公开了具有改进的共模噪声抑制的伪差分读出放大器。 读出放大器经由阵列路径连接到存储单元，并产生指示存储单元的状态的输出信号。 感测放大器包括通过阵列节点连接到阵列路径的阵列负载装置，经由参考节点连接到参考路径的参考负载装置，具有连接到参考节点的第一输入的差分级，连接到参考节点的第二输入 阵列节点和产生输出信号的输出。 感测放大器还包括连接到参考节点的平衡装置，用于在阵列节点处补偿由噪声事件引起的信号变化，并且因此减小了读出放大器在转换时的响应的延迟 发生细胞状态。