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公开(公告)号：US20240196515A1
公开(公告)日：2024-06-13
申请号：US18306874
申请日：2023-04-25
Applicant: SK hynix Inc.
Inventor： Jae Hoon LEE , Jong Wook KIM , Ju Il EOM
CPC classification number: H05K1/0213 , H05K1/09 , H05K1/111 , H05K1/115 , H05K2201/0776
Abstract: A substrate in accordance with an embodiment of the disclosure includes a signal transmission layer including a signal transmission pad and a signal transmission interconnection; a first dielectric layer stacked on the signal transmission layer; and a first reference voltage layer stacked on the first dielectric layer. The first reference voltage layer includes a first space hole and an impedance calibrator. The impedance calibrator includes an impedance calibration part disposed in the first space hole; and a first bridge connecting a first portion of the impedance calibration part to a first portion of the first reference voltage layer.
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公开(公告)号：US11751325B2
公开(公告)日：2023-09-05
申请号：US16928069
申请日：2020-07-14
Applicant: Sony Olympus Medical Solutions Inc.
Inventor： Kiyotaka Kanno
IPC: H05K1/02 , G02B23/24 , A61B1/00 , H05K1/18 , A61B1/04 , H04N23/00 , A61N1/372 , H01Q1/22 , H01Q21/28
CPC classification number: H05K1/0262 , A61B1/00124 , A61B1/04 , A61N1/37229 , G02B23/24 , H01Q1/2283 , H01Q21/28 , H04N23/00 , H05K1/0215 , H05K1/185 , H05K2201/0776
Abstract: A substrate for a medical device, a portion of which is brought into contact with or inserted into a subject. The substrate includes a patient circuit conductively connected to the portion that is configured to be brought into contact with or inserted into the subject, and a ground-side circuit configured to perform at least one of transmission of a signal, reception of a signal, and supply of electric power on the patient circuit. The ground-side circuit is grounded by a protective ground to ensure safety of a manipulator of the medical device. The substrate also includes an insulating layer between the patient circuit and the ground-side circuit providing insulation between the patient circuit and the ground-side circuit, and an isolated circuit provided apart from the patient circuit and the ground-side circuit on the insulating layer and having a different reference potential from the patient circuit and the ground-side circuit.
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公开(公告)号：US09622344B2
公开(公告)日：2017-04-11
申请号：US14391748
申请日：2013-02-28
Applicant: KABUSHIKI KAISHA NIHON MICRONICS
Inventor： Tatsuo Inoue , Takayasu Sugai , Toshiyuki Kudo , Toshinori Omori
CPC classification number: H05K1/0298 , H05K1/0233 , H05K1/0242 , H05K1/025 , H05K1/09 , H05K3/46 , H05K2201/0154 , H05K2201/0338 , H05K2201/0391 , H05K2201/0776 , H05K2201/0792 , H05K2201/083 , Y10T29/49155
Abstract: A multi-layer wiring board includes wiring layers stacked on a substrate with an insulating layer between each layer. A wire formed in the wiring layer consists of a first layer and a second layer to form a double layered structure. The first layer is made of a first conductive material and the second layer is made of a second conductive material having relative magnetic permeability of 10 or more and larger than that of the first conductive material. The characteristic impedance of the wire is adjusted to a value closer to 50 ohms than that of a wire which has the same thickness as of the wire with the double layered structure, and is made only of the first conductive material.
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公开(公告)号：US09572252B2
公开(公告)日：2017-02-14
申请号：US14444135
申请日：2014-07-28
Inventor： Tetsuyuki Tsuchida , Toshikazu Okubo , Ikuo Shohji , Takahiro Kano
IPC: B05D5/12 , B28B19/00 , C23C18/00 , H01C17/06 , H05K3/00 , H05K1/09 , C23C18/36 , C23C18/44 , C23C18/16 , H05K3/24 , C23C18/50
CPC classification number: H05K1/09 , C23C18/1651 , C23C18/36 , C23C18/44 , C23C18/50 , H05K3/243 , H05K3/244 , H05K2201/032 , H05K2201/0776 , H05K2203/072
Abstract: A wiring substrate includes an electrode including Cu or a Cu alloy, and a plated film including an electroless nickel-plated layer formed on the electrode and an electroless gold-plated layer formed on the electroless nickel-plated layer. The electroless nickel-plated layer is formed by co-precipitation of Ni, P, Bi, and S, the electroless nickel-plated layer includes a content of P of 5% by mass or more and less than 10% by mass, a content of Bi of 1 ppm by mass to 1,000 ppm by mass, and a content of S of 1 ppm by mass to 2,000 ppm by mass, and a mass ratio of the content of S to the content of Bi (S/Bi) is more than 1.0.
Abstract translation: 布线基板包括包含Cu或Cu合金的电极和形成在电极上的化学镀镍层和形成在化学镀镍层上的化学镀金层的镀膜。 化学镀镍层通过Ni，P，Bi和S的共沉淀形成，无电镀镍层的P含量为5质量％以上且小于10质量％，含量 的Bi为1质量ppm〜1000质量ppm，S为1质量ppm〜2000质量ppm，S含量与Bi（S / Bi）含量的质量比为更多 比1.0。
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公开(公告)号：US20140332259A1
公开(公告)日：2014-11-13
申请号：US14444135
申请日：2014-07-28
Inventor： Tetsuyuki TSUCHIDA , Toshikazu OKUBO , Ikuo SHOHJI , Takahiro KANO
CPC classification number: H05K1/09 , C23C18/1651 , C23C18/36 , C23C18/44 , C23C18/50 , H05K3/243 , H05K3/244 , H05K2201/032 , H05K2201/0776 , H05K2203/072
Abstract: A wiring substrate includes an electrode including Cu or a Cu alloy, and a plated film including an electroless nickel-plated layer formed on the electrode and an electroless gold-plated layer formed on the electroless nickel-plated layer. The electroless nickel-plated layer is formed by co-precipitation of Ni, P, Bi, and S, the electroless nickel-plated layer includes a content of P of 5% by mass or more and less than 10% by mass, a content of Bi of 1 ppm by mass to 1,000 ppm by mass, and a content of S of 1 ppm by mass to 2,000 ppm by mass, and a mass ratio of the content of S to the content of Bi (S/Bi) is more than 1.0.
Abstract translation: 布线基板包括包含Cu或Cu合金的电极和形成在电极上的化学镀镍层和形成在化学镀镍层上的化学镀金层的镀膜。 化学镀镍层通过Ni，P，Bi和S的共沉淀形成，无电镀镍层的P含量为5质量％以上且小于10质量％，含量 的Bi为1质量ppm〜1000质量ppm，S为1质量ppm〜2000质量ppm，S含量与Bi（S / Bi）含量的质量比为更多 比1.0。
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Patent Agency Ranking
公开(公告)号：US11924965B2
公开(公告)日：2024-03-05
申请号：US17728758
申请日：2022-04-25
Inventor： Chun-Wei Chang , Jian-Hong Lin , Shu-Yuan Ku , Wei-Cheng Liu , Yinlung Lu , Jun He
CPC classification number: H05K1/0242 , H05K1/0251 , H05K1/116 , H05K3/427 , H05K3/429 , H05K2201/0776
Abstract: A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.
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公开(公告)号：US20230345622A1
公开(公告)日：2023-10-26
申请号：US17728758
申请日：2022-04-25
Inventor： CHUN-WEI CHANG , JIAN-HONG LIN , SHU-YUAN KU , WEI-CHENG LIU , YINLUNG LU , JUN HE
CPC classification number: H05K1/0242 , H05K1/0251 , H05K1/116 , H05K3/427 , H05K3/429 , H05K2201/0776
Abstract: A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.
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18.发明授权公开(公告)号：US11678434B2
公开(公告)日：2023-06-13
申请号：US17286939
申请日：2019-11-14
Applicant: Continental Automotive France , Continental Automotive GmbH
Inventor： Daniel Guerra , Philippe Lehue
IPC: H05K1/02
CPC classification number: H05K1/0268 , H05K2201/0776 , H05K2201/09627 , H05K2201/09663 , H05K2201/09672
Abstract: A multilayer printed circuit having a control circuit including n vias that are connected in series between a first and a second electrical terminal so that an applied electric current passes at least partially through each one of the n vias. The control circuit includes track portions in each one of the layers, each one of the n vias connecting a track portion of one layer to a track portion of another layer. The control circuit includes a measurement device for measuring a potential difference across its terminals, storage for storing a threshold value and a comparator for comparing the potential difference with the threshold value so as to validate the printed circuit when the potential difference is lower than the threshold value.
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公开(公告)号：US20190098855A1
公开(公告)日：2019-04-04
申请号：US16192673
申请日：2018-11-15
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Atsushi Morishima
CPC classification number: A01H5/10 , A01H1/02 , A01H6/542 , C12N15/8245 , C12N15/8247 , C12N15/8251 , C12N15/8271 , C12N15/8274 , C12N15/8275 , C12N15/8278 , C12N15/8279 , C12N15/8286 , C12N15/8289 , H05K1/025 , H05K1/114 , H05K1/115 , H05K1/181 , H05K2201/0776 , H05K2201/09227 , H05K2201/09309 , H05K2201/09609 , H05K2201/0979
Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.
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20.发明申请公开(公告)号：US20180359854A1
公开(公告)日：2018-12-13
申请号：US16106938
申请日：2018-08-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Doh Won JUNG , Se Yun KIM , Jong Wook ROH , Jongmin LEE , Sungwoo HWANG , Jinyoung HWANG , Chan KWAK
IPC: H05K1/09 , C09D7/40 , C09D1/00 , C01G55/00 , C09D5/24 , H05K3/28 , H05K1/02 , C08K3/22 , B82Y40/00 , B82Y30/00
CPC classification number: H05K1/09 , B82Y30/00 , B82Y40/00 , C01G55/004 , C01P2002/72 , C01P2002/85 , C01P2004/03 , C01P2004/04 , C01P2004/24 , C01P2004/61 , C01P2006/40 , C08K3/22 , C09D1/00 , C09D5/24 , C09D7/70 , H05K1/0274 , H05K3/28 , H05K2201/026 , H05K2201/0302 , H05K2201/032 , H05K2201/0326 , H05K2201/0338 , H05K2201/0776 , H05K2201/10977 , Y10S977/755 , Y10S977/896 , Y10S977/932
Abstract: An electrical conductor includes a substrate; and a first conductive layer disposed on the substrate and including a plurality of metal oxide nanosheets, wherein adjacent metal oxide nanosheets of the plurality of metal oxide nanosheets contact to provide an electrically conductive path between the contacting metal oxide nanosheets, wherein the plurality of metal oxide nanosheets include an oxide of Re, V, Os, Ru, Ta, Ir, Nb, W, Ga, Mo, In, Cr, Rh, Mn, Co, Fe, or a combination thereof, and wherein the metal oxide nanosheets of the plurality of metal oxide nanosheets have an average lateral dimension of greater than or equal to about 1.1 micrometers. Also an electronic device including the electrical conductor, and a method of preparing the electrical conductor.
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