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    Circuit configurations having four terminal JFET devices
    11.
    发明授权
    Circuit configurations having four terminal JFET devices 有权
    具有四端JFET器件的电路配置

    公开(公告)号：US07804332B2

    公开(公告)日：2010-09-28

    申请号：US12506848

    申请日：2009-07-21

    Applicant: Ashok Kumar Kapoor

    Inventor： Ashok Kumar Kapoor

    IPC: H03K19/20

    CPC classification number: H01L29/8086 ,  H01L29/785 ,  H01L2029/7857 ,  H01L2924/0002 ,  H03K19/09403 ,  H01L2924/00

    Abstract: Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.

    Abstract translation: 公开了使用四端接点场效应晶体管（JFET）的电路。 这种电路可以包括各种静态和动态逻辑电路，触发器，多路复用器，三态驱动器，相位检测器，具有可变速度的逻辑，和/或具有以线性或非线性模式操作的这种四端JFET的模拟电路。

    Circuit configurations having four terminal JFET devices
    12.
    发明授权
    Circuit configurations having four terminal JFET devices 失效
    具有四端JFET器件的电路配置

    公开(公告)号：US07592841B2

    公开(公告)日：2009-09-22

    申请号：US11452442

    申请日：2006-06-13

    Applicant: Ashok Kumar Kapoor

    Inventor： Ashok Kumar Kapoor

    IPC: H03K19/20

    CPC classification number: H01L29/8086 ,  H01L29/785 ,  H01L2029/7857 ,  H01L2924/0002 ,  H03K19/09403 ,  H01L2924/00

    Abstract: Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.

    Abstract translation: 公开了使用四端接点场效应晶体管（JFET）的电路。 这种电路可以包括各种静态和动态逻辑电路，触发器，多路复用器，三态驱动器，相位检测器，具有可变速度的逻辑，和/或具有以线性或非线性模式操作的这种四端JFET的模拟电路。

    Single-rail self-resetting logic circuitry
    15.
    发明授权
    Single-rail self-resetting logic circuitry 失效
    单轨自复位逻辑电路

    公开(公告)号：US5550490A

    公开(公告)日：1996-08-27

    申请号：US450056

    申请日：1995-05-25

    Applicant: Christopher M. Durham ,  Visweswara R. Kodali ,  Salim A. Shah

    Inventor： Christopher M. Durham ,  Visweswara R. Kodali ,  Salim A. Shah

    IPC: H03K3/355 ,  H03K19/094 ,  H03K19/096 ,  H03K19/00

    CPC classification number: H03K3/355 ,  H03K19/09403 ,  H03K19/0966

    Abstract: A forward single-rail self-resetting reset circuit is utilized to reset a logic circuit to a selected state subsequent to each iteration of a logical operation on inputted data into the logic circuit. The reset circuit receives at least one of the data inputs and its complement signal so that the reset signal produced by the reset circuit is activated regardless of the voltage level of the data input signals.

    Abstract translation: 在对逻辑电路的输入数据进行逻辑运算的每次重复之后，利用正向单轨自复位复位电路将逻辑电路复位到选定状态。 复位电路接收数据输入及其补码信号中的至少一个，使得复位电路产生的复位信号无论数据输入信号的电压电平如何被激活。

    Output circuit having three power supply lines
    16.
    发明授权
    Output circuit having three power supply lines 失效
    输出电路有三条电源线

    公开(公告)号：US5436487A

    公开(公告)日：1995-07-25

    申请号：US248729

    申请日：1994-05-25

    Applicant: Kaoru Narita

    Inventor： Kaoru Narita

    IPC: H01L21/822 ,  G11C11/409 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H03K5/02 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/094 ,  H01L27/02 ,  H01L29/72

    CPC classification number: H03K19/09403 ,  H03K19/00315 ,  H03K19/00361

    Abstract: In an output circuit having first and second MOS transistors in series between a first power supply line and a second power supply line, and a third MOS transistor, the gates of the first and second transistors are connected to first and second input nodes, respectively, and an output node is provided between the first and second MOS transistors. The third MOS transistor is connected between one of the input nodes and the output node. The gate of the third MOS transistor is connected to a third power supply line.

    Abstract translation: 在具有串联在第一电源线和第二电源线之间的第一和第二MOS晶体管和第三MOS晶体管的输出电路中，第一和第二晶体管的栅极分别连接到第一和第二输入节点， 并且在第一和第二MOS晶体管之间提供输出节点。 第三MOS晶体管连接在输入节点之一和输出节点之间。 第三MOS晶体管的栅极连接到第三电源线。

    Semiconductor switching element
    17.
    发明授权
    Semiconductor switching element 失效
    半导体开关元件

    公开(公告)号：US3657616A

    公开(公告)日：1972-04-18

    申请号：US3657616D

    申请日：1969-12-15

    Applicant: NIPPON TELEGRAPH & TELEPHONE

    Inventor： MIZUSHIMA YOSHIHIKO ,  SUDO TSUNETA

    IPC: H01L27/146 ,  H01L27/102 ,  H01L29/00 ,  H01L29/74 ,  H03K17/693 ,  H03K19/08 ,  H03K19/094 ,  H01L11/08

    CPC classification number: H03K19/09403 ,  H01L27/1028 ,  H01L29/00 ,  H03K17/693 ,  H03K19/08

    Abstract: A semiconductor switching element which comprises at least one collector region diffused in a semiconductor substrate from its surface, the collector region containing a high concentration of impurities imparting thereto the same type of conductivity as the substrate and displaying a higher degree of conductivity than the substrate and being formed into a fully narrow area, a base region diffused at a space of approximately 50 microns max. from the collector region, as measured from the same surface of the substrate as that on which there is formed the collector region, such that the edge of the base region facing the collector region is sufficiently longer than that of the collector region, the base region containing a high concentration of impurities imparting thereto the same type of conductivity as the semiconductor substrate and displaying a higher degree of conductivity than the substrate, and at least one emitter region diffused from the same surface of the substrate as that through which the aforesaid two regions are diffused and having an opposite type of conductivity as the substrate.

    Abstract translation: 一种半导体开关元件，其包括从其表面扩散到半导体衬底中的至少一个集电极区域，所述集电极区域含有高浓度的杂质，赋予与衬底相同的导电性并且显示比衬底更高的导电性， 形成为完全狭窄的区域，在最大约50微米的空间扩散的基极区域。 从与集电极区域相同的与基板相同的表面测定的集电极区域，使得面对集电极区域的基极区域的边缘比集电极区域的边缘充分长，基极区域 含有高浓度的杂质赋予其与半导体衬底相同类型的导电性并且显示出比衬底更高的导电性，以及至少一个发射极区域与衬底的与上述两个区域相同的表面扩散 被扩散并具有与衬底相反的导电性。

    ASYMMETRICAL BUS KEEPER
    18.
    发明申请
    ASYMMETRICAL BUS KEEPER 有权
    不对称总线保持器

    公开(公告)号：US20130285703A1

    公开(公告)日：2013-10-31

    申请号：US13927519

    申请日：2013-06-26

    Applicant: RESEARCH IN MOTION LIMITED

    Inventor： John Douglas McGinn

    IPC: H03K19/0185 ,  H03K19/018 ,  H03K19/0175

    CPC classification number: H03K19/018507 ,  H03K19/017509 ,  H03K19/01806 ,  H03K19/082 ,  H03K19/09403

    Abstract: Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first inverter stage having an input node and an output node, an asymmetrical inverter stage having an input node and an output node and a feedback stage with an input node and an output node. The input node of the asymmetrical inverter stage is connected to the output node of the first inverter stage. The input node of the feedback stage connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage connected to the input node of the first inverter stage. The asymmetrical stage provides asymmetrical drive towards one logic level.

    Abstract translation: 这里描述了用于向一个逻辑电平提供不对称驱动的非对称总线保持器电路的各种实施例。 非对称总线保持器电路包括具有输入节点和输出节点的第一反相器级，具有输入节点和输出节点的非对称逆变器级和具有输入节点和输出节点的反馈级。 不对称反相器级的输入节点连接到第一反相器级的输出节点。 反馈级的输入节点连接到非对称逆变器级的输出节点，反馈级的输出节点连接到第一级逆变器级的输入节点。 非对称阶段向一个逻辑水平提供不对称驱动。

    ASYMMETRICAL BUS KEEPER
    19.
    发明申请
    ASYMMETRICAL BUS KEEPER 有权

    公开(公告)号：US20130093465A1

    公开(公告)日：2013-04-18

    申请号：US13398929

    申请日：2012-02-17

    Applicant: John Douglas McGinn

    Inventor： John Douglas McGinn

    IPC: H03K19/094 ,  H03K19/082 ,  H03K19/0175

    CPC classification number: H03K19/018507 ,  H03K19/017509 ,  H03K19/01806 ,  H03K19/082 ,  H03K19/09403

    Abstract: Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first inverter stage having an input node and an output node, an asymmetrical inverter stage having an input node and an output node and a feedback stage with an input node and an output node. The input node of the asymmetrical inverter stage is connected to the output node of the first inverter stage. The input node of the feedback stage connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage connected to the input node of the first inverter stage. The asymmetrical stage provides asymmetrical drive towards one logic level.

    Circuit configurations having four terminal devices
    20.
    发明授权
    Circuit configurations having four terminal devices 有权
    具有四个终端设备的电路配置

    公开(公告)号：US07986167B2

    公开(公告)日：2011-07-26

    申请号：US12861659

    申请日：2010-08-23

    Applicant: Ashok Kumar Kapoor

    Inventor： Ashok Kumar Kapoor

    IPC: H03K19/20

    CPC classification number: H01L29/8086 ,  H01L29/785 ,  H01L2029/7857 ,  H01L2924/0002 ,  H03K19/09403 ,  H01L2924/00

    Abstract: Circuits using four terminal transistors are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal transistors operating in a linear or nonlinear mode.

    Abstract translation: 公开了使用四个端子晶体管的电路。 这种电路可以包括各种静态和动态逻辑电路，触发器，多路复用器，三态驱动器，相位检测器，具有可变速度操作的逻辑，和/或具有以线性或非线性模式操作的这种四端子晶体管的模拟电路。

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