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    Current source logic gate
    2.
    发明授权
    Current source logic gate 有权

    公开(公告)号：US09755645B1

    公开(公告)日：2017-09-05

    申请号：US15373689

    申请日：2016-12-09

    Applicant: The United States of America as represented by the Administrator of NASA

    Inventor： Michael J. Krasowski ,  Norman F. Prokop

    IPC: H03K19/20 ,  H03K19/0952 ,  H03K19/094

    CPC classification number: H03K19/0952 ,  H03K19/09403 ,  H03K19/09407 ,  H03K19/20

    Abstract: A current source logic gate with depletion mode field effect transistor (“FET”) transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

    Asymmetrical bus keeper
    3.
    发明授权
    Asymmetrical bus keeper 有权

    公开(公告)号：US08508250B2

    公开(公告)日：2013-08-13

    申请号：US13398929

    申请日：2012-02-17

    Applicant: John Douglas McGinn

    Inventor： John Douglas McGinn

    IPC: H03K17/16

    CPC classification number: H03K19/018507 ,  H03K19/017509 ,  H03K19/01806 ,  H03K19/082 ,  H03K19/09403

    Abstract: Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first inverter stage having an input node and an output node, an asymmetrical inverter stage having an input node and an output node and a feedback stage with an input node and an output node. The input node of the asymmetrical inverter stage is connected to the output node of the first inverter stage. The input node of the feedback stage connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage connected to the input node of the first inverter stage. The asymmetrical stage provides asymmetrical drive towards one logic level.

    N channel JFET based digital logic gate structure
    4.
    发明授权
    N channel JFET based digital logic gate structure 有权
    基于N沟道JFET的数字逻辑门结构

    公开(公告)号：US08416007B1

    公开(公告)日：2013-04-09

    申请号：US13098918

    申请日：2011-05-02

    Applicant: Michael J Krasowski

    Inventor： Michael J Krasowski

    IPC: H03K17/687

    CPC classification number: H03K19/09403 ,  H03K17/6871 ,  H03K2217/0036

    Abstract: An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.

    Abstract translation: 提供了一种装置，其包括具有连接到零电压的源极的第一场效应晶体管和通过第一电阻器连接到电压漏极漏极（Vdd）的漏极。 该装置还包括第一节点，其被配置为将第二电阻器连接到第三电阻器并且连接到第一场效应晶体管的栅极的输入，以使第一场效应晶体管接收信号。 该装置还包括被配置为单位增益缓冲器的第二场效应晶体管，其具有连接到Vdd的漏极和未提供的源极。

    "> Circuit element on a single ended interconnection for generating a logical output finish/clock signal when detecting a state change to logical
    5.
    发明授权
    Circuit element on a single ended interconnection for generating a logical output finish/clock signal when detecting a state change to logical "1 or 0". 失效
    在单端互连上的电路元件，用于当检测到状态改变为逻辑“1或0”时产生逻辑输出完成/时钟信号。

    公开(公告)号：US5675774A

    公开(公告)日：1997-10-07

    申请号：US449448

    申请日：1995-05-24

    Applicant: John Atkinson Fifield ,  Lawrence Griffith Heller

    Inventor： John Atkinson Fifield ,  Lawrence Griffith Heller

    IPC: H03K19/094 ,  G06F1/04

    CPC classification number: H03K19/09403

    Abstract: Disclosed is a Data Valid/Finish circuit element, an integrated circuit using the element, and a method of using the element. The circuit element, which may be incorporated in high speed, digital integrated circuit chips, has an input for receiving input from a data stream, and outputs. One of the outputs is an output true for generating a logical "1" when the input is a logical "1". The other output is an output complementary means for generating a logical "1" when the input is a logical "0". The system logically combines the outputs through an output finish/clock for receiving and combining the outputs of the output true and the output complementary. This generates a logical signal when the input from the data stream is either a logical "0" or a logical "1".

    Abstract translation: 公开了一种数据有效/完成电路元件，使用该元件的集成电路以及使用该元件的方法。 可以并入高速数字集成电路芯片的电路元件具有用于从数据流接收输入并输出的输入。 当输入为逻辑“1”时，输出之一是产生逻辑“1”的输出。 另一个输出是当输入为逻辑“0”时产生逻辑“1”的输出互补装置。 该系统通过输出完成/时钟逻辑组合输出，用于接收和组合输出true和输出互补的输出。 当来自数据流的输入是逻辑“0”或逻辑“1”时，这产生逻辑信号。

    Asymmetrical bus keeper
    6.
    发明授权
    Asymmetrical bus keeper 有权
    不对称巴士管理员

    公开(公告)号：US09209808B2

    公开(公告)日：2015-12-08

    申请号：US13927519

    申请日：2013-06-26

    Applicant: BLACKBERRY LIMITED

    Inventor： John Douglas McGinn

    IPC: H03K17/16 ,  H03K19/0185 ,  H03K19/082 ,  H03K19/018 ,  H03K19/094 ,  H03K19/0175

    CPC classification number: H03K19/018507 ,  H03K19/017509 ,  H03K19/01806 ,  H03K19/082 ,  H03K19/09403

    Abstract: Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first inverter stage having an input node and an output node, an asymmetrical inverter stage having an input node and an output node and a feedback stage with an input node and an output node. The input node of the asymmetrical inverter stage is connected to the output node of the first inverter stage. The input node of the feedback stage connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage connected to the input node of the first inverter stage. The asymmetrical stage provides asymmetrical drive towards one logic level.

    Abstract translation: 这里描述了用于向一个逻辑电平提供不对称驱动的非对称总线保持器电路的各种实施例。 非对称总线保持器电路包括具有输入节点和输出节点的第一反相器级，具有输入节点和输出节点的非对称逆变器级和具有输入节点和输出节点的反馈级。 不对称反相器级的输入节点连接到第一反相器级的输出节点。 反馈级的输入节点连接到非对称逆变器级的输出节点，反馈级的输出节点连接到第一级逆变器级的输入节点。 非对称阶段向一个逻辑水平提供不对称驱动。

    Circuit Configurations Having Four Terminal JFET Devices
    7.
    发明申请
    Circuit Configurations Having Four Terminal JFET Devices 有权
    具有四个端子JFET器件的电路配置

    公开(公告)号：US20090278570A1

    公开(公告)日：2009-11-12

    申请号：US12506848

    申请日：2009-07-21

    Applicant: Ashok Kumar Kapoor

    Inventor： Ashok Kumar Kapoor

    IPC: H03K19/094

    CPC classification number: H01L29/8086 ,  H01L29/785 ,  H01L2029/7857 ,  H01L2924/0002 ,  H03K19/09403 ,  H01L2924/00

    Abstract: Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.

    Abstract translation: 公开了使用四端接点场效应晶体管（JFET）的电路。 这种电路可以包括各种静态和动态逻辑电路，触发器，多路复用器，三态驱动器，相位检测器，具有可变速度的逻辑，和/或具有以线性或非线性模式操作的这种四端JFET的模拟电路。

    Circuit configurations having four terminal JFET devices
    8.
    发明申请
    Circuit configurations having four terminal JFET devices 失效
    具有四端JFET器件的电路配置

    公开(公告)号：US20070262793A1

    公开(公告)日：2007-11-15

    申请号：US11452442

    申请日：2006-06-13

    Applicant: Ashok Kumar Kapoor

    Inventor： Ashok Kumar Kapoor

    IPC: H03K19/00 ,  H01L25/00

    CPC classification number: H01L29/8086 ,  H01L29/785 ,  H01L2029/7857 ,  H01L2924/0002 ,  H03K19/09403 ,  H01L2924/00

    Abstract: Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.

    Abstract translation: 公开了使用四端接点场效应晶体管（JFET）的电路。 这种电路可以包括各种静态和动态逻辑电路，触发器，多路复用器，三态驱动器，相位检测器，具有可变速度的逻辑，和/或具有以线性或非线性模式操作的这种四端JFET的模拟电路。

    Cascade FET logic circuits
    9.
    发明授权
    Cascade FET logic circuits 失效
    级联FET逻辑电路

    公开(公告)号：US4877976A

    公开(公告)日：1989-10-31

    申请号：US257897

    申请日：1988-10-13

    Applicant: Lawrence E. Lach ,  Mikiharu Ohoka

    Inventor： Lawrence E. Lach ,  Mikiharu Ohoka

    IPC: H03K19/094 ,  H03K19/0952

    CPC classification number: H03K19/0952 ,  H03K19/09403

    Abstract: A group III-V digital logic circuit which includes either at least two enhancement type metal semiconductor field effect transistors and one load element or two first type field effect transistors having a first threshold voltage and two second type field effect transistors having a second threshold voltage, for providing a logic operation. The second threshold voltage is less than zero and is less than the first threshold voltage. The group III-V digital logic circuit can be formed as an integrated circuit on, in particular, a GaAs substrate. The field effect transistor can be either a metal semiconductor field effect transistor or a junction field effect transistor.

    Abstract translation: 一种III-V族数字逻辑电路，其包括至少两个增强型金属半导体场效应晶体管和一个具有第一阈值电压的负载元件或两个第一类型场效应晶体管和具有第二阈值电压的两个第二类型场效应晶体管， 用于提供逻辑运算。 第二阈值电压小于零并且小于第一阈值电压。 III-V族数字逻辑电路可以形成为特别是GaAs衬底上的集成电路。 场效应晶体管可以是金属半导体场效应晶体管或结型场效应晶体管。

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