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    Low-current logic-gate circuit
    1.
    发明授权
    Low-current logic-gate circuit 有权
    低电流逻辑门电路

    公开(公告)号：US08653854B2

    公开(公告)日：2014-02-18

    申请号：US13321117

    申请日：2010-06-15

    Applicant: Erwin Spits ,  Léon C. M. van den Oever

    Inventor： Erwin Spits ,  Léon C. M. van den Oever

    IPC: H03K19/094

    CPC classification number: H03K19/09418 ,  H03K19/09407 ,  H03K19/09445

    Abstract: A circuit includes E-mode transistors with gate-source junction, a D-mode transistor with gate-source junction. A component generates a voltage drop between the source of the D-mode transistor and the drain of an E mode transistor provided as a signal output. A connection is made between this drain of the E-mode transistor and the gate of the D-mode transistor, and a signal input at the gates of the E-mode transistors.

    Abstract translation: 电路包括具有栅极 - 源极结的E型晶体管，具有栅极 - 源极结的D型晶体管。 一个分量在D模式晶体管的源极和作为信号输出端提供的E模式晶体管的漏极之间产生一个电压降。 在E模式晶体管的漏极和D模式晶体管的栅极之间进行连接，并在E模式晶体管的栅极处输入信号。

    Low-current inverter circuit
    2.
    发明授权
    Low-current inverter circuit 有权
    低电流逆变电路

    公开(公告)号：US08610464B2

    公开(公告)日：2013-12-17

    申请号：US13321128

    申请日：2010-06-15

    Applicant: Erwin Spits

    Inventor： Erwin Spits

    IPC: H03K19/094

    CPC classification number: H03K19/09418 ,  H03K19/09407 ,  H03K19/09445

    Abstract: The circuit includes an E-mode transistor with gate-source junction, a D-mode transistor with gate-source junction, a component generating a voltage drop between the source of the D-mode transistor and the drain of the E-mode transistor, and a connection between the drain of the E-mode transistor and the gate of the D-mode transistor. The gate of the E-mode transistor is provided for an input signal, and the drain of the E-mode transistor is provided for an output signal.

    Abstract translation: 该电路包括具有栅极 - 源极结的E型晶体管，具有栅极 - 源极结的D型晶体管，在D型晶体管的源极和E型晶体管的漏极之间产生电压降的分量， 以及E型晶体管的漏极与D型晶体管的栅极之间的连接。 E模式晶体管的栅极被提供用于输入信号，并且E模式晶体管的漏极被提供用于输出信号。

    Inverter and logic device comprising the same
    3.
    发明申请
    Inverter and logic device comprising the same 有权

    公开(公告)号：US20100295579A1

    公开(公告)日：2010-11-25

    申请号：US12805402

    申请日：2010-07-29

    Applicant: Sun-il Kim ,  Chang-jung Kim ,  Sang-wook Kim

    Inventor： Sun-il Kim ,  Chang-jung Kim ,  Sang-wook Kim

    IPC: H03K19/094

    CPC classification number: H03K19/09443 ,  H03K19/09407

    Abstract: The inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses. The channel region of the driving transistor may be thinner than the channel region of the load transistor. A channel layer of the driving transistor may have a recessed region between a source and a drain which contact both ends of the channel layer. The driving transistor may be an enhancement mode transistor and the load transistor may be a depletion mode transistor.

    Logic circuit and display device having the same
    5.
    发明授权
    Logic circuit and display device having the same 有权
    具有相同的逻辑电路和显示装置

    公开(公告)号：US08786313B2

    公开(公告)日：2014-07-22

    申请号：US13585120

    申请日：2012-08-14

    Applicant: Daisuke Kawae

    Inventor： Daisuke Kawae

    IPC: H01L25/00 ,  H03K19/00 ,  H03K19/20

    CPC classification number: H03K19/09407 ,  G02F1/1362 ,  G02F1/167 ,  G02F2001/1674

    Abstract: It is an object to provide a logic circuit which can be operated even when unipolar transistors are used. A logic circuit includes a source follower circuit and a logic circuit an input portion of which is connected to an output portion of the source follower circuit and all transistors are unipolar transistors. A potential of a wiring for supplying a low potential connected to the source follower circuit is lower than a potential of a wiring for supplying a low potential connected to the logic circuit which includes unipolar transistors. In this manner, a logic circuit which can be operated even with unipolar depletion transistors can be provided.

    Abstract translation: 本发明的目的是提供即使在使用单极晶体管时也可以进行操作的逻辑电路。 逻辑电路包括源极跟随器电路和逻辑电路，其输入部分连接到源极跟随器电路的输出部分，所有晶体管都是单极晶体管。 用于提供连接到源极跟随器电路的低电位的布线的电位低于用于提供连接到包括单极晶体管的逻辑电路的低电位的布线的电位。 以这种方式，可以提供甚至可以用单极耗尽晶体管操作的逻辑电路。

    Low-Current Logic Plus Driver Circuit
    6.
    发明申请
    Low-Current Logic Plus Driver Circuit 有权
    低电流逻辑加驱动电路

    公开(公告)号：US20120268166A1

    公开(公告)日：2012-10-25

    申请号：US13457244

    申请日：2012-04-26

    Applicant: Léon C.M. van den Oever ,  Erwin Spits

    Inventor： Léon C.M. van den Oever ,  Erwin Spits

    IPC: H03K19/094

    CPC classification number: H03K19/09421 ,  H03K19/09407 ,  H03K19/0952

    Abstract: A circuit includes a logic stage, an inverter stage, and a driver stage. The logic stage and the inverter stage are provided with current limiters, which include a D-mode feedback transistor and a component that generates a voltage drop. A feedback loop connects the source and the gate of the D-mode feedback transistor via this component. The driver stage includes E-mode transistors connected in a totem pole that drive a D-mode transistor and an E-mode transistor to connect and disconnect the load circuit.

    Abstract translation: 电路包括逻辑级，反相器级和驱动级。 逻辑级和反相器级配有限流器，其包括D型反馈晶体管和产生电压降的元件。 反馈环路通过该部件连接D模式反馈晶体管的源极和栅极。 驱动器级包括连接在图腾柱中的E型晶体管，其驱动D模式晶体管和E模式晶体管以连接和断开负载电路。

    Direct coupled semiconductor logic circuit
    7.
    发明授权
    Direct coupled semiconductor logic circuit 失效
    直接耦合半导体逻辑电路

    公开(公告)号：US4752701A

    公开(公告)日：1988-06-21

    申请号：US65149

    申请日：1987-06-12

    Applicant: Katsuaki Gonoi

    Inventor： Katsuaki Gonoi

    IPC: H03K19/0952 ,  H03K19/017 ,  H03K19/094 ,  H03K3/33 ,  H03K5/08 ,  H03K19/12

    CPC classification number: H03K19/01707 ,  H03K19/09407

    Abstract: In a semiconductor logic circuit, a plurality of gates are provided, each formed of a junction type field effect transistor. The junction type field effect transistor of one of the gates is directly coupled to the junction type field effect transistor of a succeeding gate. An element is provided for clamping an output voltage of the junction type field effect transistor of the one gate, which provides an input voltage for the junction type field effect transistor of the succeeding gate, to below about a forward voltage of a pn junction of the succeeding gate.

    Abstract translation: 在半导体逻辑电路中，提供多个栅极，每个栅极由结型场效应晶体管形成。 其中一个栅极的结型场效应晶体管直接耦合到后续栅极的结型场效应晶体管。 提供了一个元件，用于钳位一个栅极的结型场效应晶体管的输出电压，该输出电压为后续栅极的结型场效应晶体管提供一个输入电压，低于该栅极的pn结的正向电压 后门

    POWER SWITCHING CELL WITH NORMALLY CONDUCTING FIELD-EFFECT TRANSISTORS
    10.
    发明申请
    POWER SWITCHING CELL WITH NORMALLY CONDUCTING FIELD-EFFECT TRANSISTORS 审中-公开
    具有正常导通场效应晶体管的电源开关单元

    公开(公告)号：US20170047924A1

    公开(公告)日：2017-02-16

    申请号：US15306027

    申请日：2015-04-17

    Applicant: THALES ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  UNIVERSITE DE LIMOGES ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE

    Inventor： Olivier JARDEL ,  Raymond QUERE ,  Stéphane PIOTROWICZ ,  Philippe BOUYSSE ,  Sylvain DELAGE ,  Audrey MARTIN

    IPC: H03K17/687 ,  H03K17/041

    CPC classification number: H03K17/687 ,  H03K17/04106 ,  H03K19/09407

    Abstract: A power switching cell with normally on field-effect transistors comprises a current switch receiving the control input signal over an activation input and a power transistor for switching a high voltage VDD applied to its drain, to its source that is connected to the output port of the cell. The control of the gate of the power transistor whose source is floating, according to the input signal, is provided by a self-biasing circuit connected between its gate and source. The current switch is connected between the self-biasing circuit and a zero or negative reference voltage. The self-biasing circuit comprises a transistor whose source or drain is connected to the gate or source of the power transistor. The gate of this transistor is biased by a resistor connected between its gate and source, and between the current switch and the source. The transistors are HEMT transistors using GaN or AsGa technology.

    Abstract translation: 具有通常场效应晶体管的功率开关单元包括通过激活输入接收控制输入信号的电流开关和用于将施加到其漏极的高电压VDD切换到其源极的功率晶体管，其连接到输出端口 细胞。 源极浮动的功率晶体管的栅极根据输入信号的控制由连接在其栅极和源极之间的自偏置电路提供。 电流开关连接在自偏置电路和零或负参考电压之间。 自偏置电路包括其源极或漏极连接到功率晶体管的栅极或源极的晶体管。 该晶体管的栅极由连接在其栅极和源极之间以及电流开关和源极之间的电阻器偏置。 晶体管是使用GaN或AsGa技术的HEMT晶体管。

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