公开(公告)号：US20110210714A1

公开(公告)日：2011-09-01

申请号：US13040733

申请日：2011-03-04

Applicant: Erwin Spits

Inventor： Erwin Spits

IPC: G05F3/02

CPC classification number: G05F3/227

Abstract: A circuit includes a supply voltage and a control current line including two resistors. A sink current line branches off from the control current line between the resistors. A current sink transistor has an emitter that is connected to the sink current line and a collector that is connected to ground via a first further resistor. At least one reference transistor has an emitter that is connected to its base, to the supply voltage via a second further resistor and to the base of the current sink transistor. The collector of the reference transistor is connected to ground or to an emitter of a further reference transistor, which is switched in a manner similar to the first reference transistor.

Abstract translation: 电路包括电源电压和包括两个电阻器的控制电流线。 汇流电流线从电阻之间的控制电流线分支。 电流吸收晶体管具有连接到吸收电流线的发射极和经由第一另外的电阻器连接到地的集电极。 至少一个参考晶体管具有通过第二另外的电阻器和电流吸收晶体管的基极连接到其基极的发射极到电源电压。 参考晶体管的集电极连接到另一参考晶体管的接地或发射极，其以类似于第一参考晶体管的方式被切换。

公开(公告)号：US08912847B2

公开(公告)日：2014-12-16

申请号：US13513239

申请日：2009-12-03

Applicant: Erwin Spits ,  Leon C. M. van den Oever

Inventor： Erwin Spits ,  Leon C. M. van den Oever

IPC: H03F3/68

CPC classification number: H03F3/24 ,  H03F1/0277 ,  H03F3/602 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/429 ,  H03F2200/543 ,  H03F2203/7209 ,  H03F2203/7239 ,  H04B1/0483 ,  H04B2001/0408

Abstract: A power amplifier circuit (DIPPA), comprising a driver stage (DR) which is applicable to provide a preamplified driver signal (S_DR) dependent on a predetermined transmit signal. The power amplifier circuit (DIPPA) comprises also a frequency selector (DIP) which is electrically coupled to the driver stage (DR) and which is applicable to separate the driver signal (S_DR) into a first and second signal (S—1, S—2). The first signal (S—1) is associated to a first predetermined and the second signal (S—2) is associated to a second predetermined frequency band. The power amplifier circuit (DIPPA) comprises at least a first and second power amplifier stage (PA1, PA2). The first and second power amplifier stage (PA1, PA2) are electrically coupled to the frequency selector (DIP). The first and second power amplifier stage (PA1, PA2) is operable to provide a first and second amplified signal (S_A1, S—2), respectively, dependent on the first and second signal (S—1, S—2), respectively.

Abstract translation: 一种功率放大器电路（DIPPA），包括驱动级（DR），其可应用于提供取决于预定发射信号的预放大驱动器信号（S_DR）。 功率放大器电路（DIPPA）还包括频率选择器（DIP），其被电耦合到驱动级（DR），并且可应用于将驱动器信号（S_DR）分离成第一和第二信号（S-1，S -2）。 第一信号（S-1）与第一预定相关联，第二信号（S-2）与第二预定频带相关联。 功率放大器电路（DIPPA）至少包括第一和第二功率放大器级（PA1，PA2）。 第一和第二功率放大器级（PA1，PA2）电耦合到频率选择器（DIP）。 第一和第二功率放大器级（PA1，PA2）可分别根据第一和第二信号（S-1，S-2）分别提供第一和第二放大信号（S_A1，S-2） 。

公开(公告)号：US08653854B2

公开(公告)日：2014-02-18

申请号：US13321117

申请日：2010-06-15

Applicant: Erwin Spits ,  Léon C. M. van den Oever

Inventor： Erwin Spits ,  Léon C. M. van den Oever

IPC: H03K19/094

CPC classification number: H03K19/09418 ,  H03K19/09407 ,  H03K19/09445

Abstract: A circuit includes E-mode transistors with gate-source junction, a D-mode transistor with gate-source junction. A component generates a voltage drop between the source of the D-mode transistor and the drain of an E mode transistor provided as a signal output. A connection is made between this drain of the E-mode transistor and the gate of the D-mode transistor, and a signal input at the gates of the E-mode transistors.

Abstract translation: 电路包括具有栅极 - 源极结的E型晶体管，具有栅极 - 源极结的D型晶体管。 一个分量在D模式晶体管的源极和作为信号输出端提供的E模式晶体管的漏极之间产生一个电压降。 在E模式晶体管的漏极和D模式晶体管的栅极之间进行连接，并在E模式晶体管的栅极处输入信号。

公开(公告)号：US08610464B2

公开(公告)日：2013-12-17

申请号：US13321128

申请日：2010-06-15

Applicant: Erwin Spits

Inventor： Erwin Spits

IPC: H03K19/094

CPC classification number: H03K19/09418 ,  H03K19/09407 ,  H03K19/09445

Abstract: The circuit includes an E-mode transistor with gate-source junction, a D-mode transistor with gate-source junction, a component generating a voltage drop between the source of the D-mode transistor and the drain of the E-mode transistor, and a connection between the drain of the E-mode transistor and the gate of the D-mode transistor. The gate of the E-mode transistor is provided for an input signal, and the drain of the E-mode transistor is provided for an output signal.

Abstract translation: 该电路包括具有栅极 - 源极结的E型晶体管，具有栅极 - 源极结的D型晶体管，在D型晶体管的源极和E型晶体管的漏极之间产生电压降的分量， 以及E型晶体管的漏极与D型晶体管的栅极之间的连接。 E模式晶体管的栅极被提供用于输入信号，并且E模式晶体管的漏极被提供用于输出信号。

公开(公告)号：US08258858B2

公开(公告)日：2012-09-04

申请号：US13040733

申请日：2011-03-04

Applicant: Erwin Spits

Inventor： Erwin Spits

IPC: G05F1/10

CPC classification number: G05F3/227

Abstract: A circuit includes a supply voltage and a control current line including two resistors. A sink current line branches off from the control current line between the resistors. A current sink transistor has an emitter that is connected to the sink current line and a collector that is connected to ground via a first further resistor. At least one reference transistor has an emitter that is connected to its base, to the supply voltage via a second further resistor and to the base of the current sink transistor. The collector of the reference transistor is connected to ground or to an emitter of a further reference transistor, which is switched in a manner similar to the first reference transistor.

Abstract translation: 电路包括电源电压和包括两个电阻器的控制电流线。 汇流电流线从电阻之间的控制电流线分支。 电流吸收晶体管具有连接到吸收电流线的发射极和经由第一另外的电阻器连接到地的集电极。 至少一个参考晶体管具有通过第二另外的电阻器和电流吸收晶体管的基极连接到其基极的发射极到电源电压。 参考晶体管的集电极连接到另一参考晶体管的接地或发射极，其以类似于第一参考晶体管的方式被切换。

公开(公告)号：US08686752B2

公开(公告)日：2014-04-01

申请号：US13457244

申请日：2012-04-26

Applicant: Léon C. M. van den Oever ,  Erwin Spits

Inventor： Léon C. M. van den Oever ,  Erwin Spits

IPC: H03K19/094

CPC classification number: H03K19/09421 ,  H03K19/09407 ,  H03K19/0952

Abstract: A circuit includes a logic stage, an inverter stage, and a driver stage. The logic stage and the inverter stage are provided with current limiters, which include a D-mode feedback transistor and a component that generates a voltage drop. A feedback loop connects the source and the gate of the D-mode feedback transistor via this component. The driver stage includes E-mode transistors connected in a totem pole that drive a D-mode transistor and an E-mode transistor to connect and disconnect the load circuit.

Abstract translation: 电路包括逻辑级，反相器级和驱动级。 逻辑级和反相器级配有限流器，其包括D型反馈晶体管和产生电压降的元件。 反馈环路通过该部件连接D模式反馈晶体管的源极和栅极。 驱动器级包括连接在图腾柱中的E型晶体管，其驱动D模式晶体管和E模式晶体管以连接和断开负载电路。

公开(公告)号：US08436663B2

公开(公告)日：2013-05-07

申请号：US13322367

申请日：2010-06-21

Applicant: Erwin Spits ,  Léon C. M. van den Oever

Inventor： Erwin Spits ,  Léon C. M. van den Oever

IPC: H03K3/00

CPC classification number: H03K19/018521

Abstract: A current-limited differential entry stage compares an input signal to a reference voltage generated by a current-limited transistor or diode configuration. Current limiters comprise a D-mode feedback transistor having a gate-source junction. The D-mode transistor is not conducting between the source and the drain if a gate-source voltage is more negative than a negative threshold voltage, and conducting between the source and the drain, otherwise a feedback connection connects the source of the D-mode feedback transistor to its gate via a component that generates a voltage drop.

Abstract translation: 限流差分输入级将输入信号与由限流晶体管或二极管配置产生的参考电压进行比较。 电流限制器包括具有栅极 - 源极结的D型反馈晶体管。 如果栅源电压比负阈值电压更负，并且在源极和漏极之间导通，则D模式晶体管在源极和漏极之间不导通，否则反馈连接将D模式的源 反馈晶体管通过产生电压降的元件到其栅极。

公开(公告)号：US20120235735A1

公开(公告)日：2012-09-20

申请号：US13513239

申请日：2009-12-03

Applicant: Erwin Spits ,  Leon C.M. van den Oever

Inventor： Erwin Spits ,  Leon C.M. van den Oever

IPC: H03G3/00

CPC classification number: H03F3/24 ,  H03F1/0277 ,  H03F3/602 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/429 ,  H03F2200/543 ,  H03F2203/7209 ,  H03F2203/7239 ,  H04B1/0483 ,  H04B2001/0408

Abstract: A power amplifier circuit (DIPPA), comprising a driver stage (DR) which is applicable to provide a preamplified driver signal (S_DR) dependent on a predetermined transmit signal. The power amplifier circuit (DIPPA) comprises also a frequency selector (DIP) which is electrically coupled to the driver stage (DR) and which is applicable to separate the driver signal (S_DR) into a first and second signal (S—1, S—2). The first signal (S—1) is associated to a first predetermined and the second signal (S—2) is associated to a second predetermined frequency band. The power amplifier circuit (DIPPA) comprises at least a first and second power amplifier stage (PA1, PA2). The first and second power amplifier stage (PA1, PA2) are electrically coupled to the frequency selector (DIP). The first and second power amplifier stage (PA1, PA2) is operable to provide a first and second amplified signal (S_A1, S—2), respectively, dependent on the first and second signal (S—1, S—2), respectively.

Abstract translation: 一种功率放大器电路（DIPPA），包括驱动级（DR），其可应用于提供取决于预定发射信号的预放大驱动器信号（S_DR）。 功率放大器电路（DIPPA）还包括频率选择器（DIP），其被电耦合到驱动级（DR），并且可应用于将驱动器信号（S_DR）分离成第一和第二信号（S-1，S -2）。 第一信号（S-1）与第一预定相关联，第二信号（S-2）与第二预定频带相关联。 功率放大器电路（DIPPA）至少包括第一和第二功率放大器级（PA1，PA2）。 第一和第二功率放大器级（PA1，PA2）电耦合到频率选择器（DIP）。 第一和第二功率放大器级（PA1，PA2）可分别根据第一和第二信号（S-1，S-2）分别提供第一和第二放大信号（S_A1，S-2） 。

公开(公告)号：US20120127767A1

公开(公告)日：2012-05-24

申请号：US13321128

申请日：2010-06-15

Applicant: Erwin Spits

Inventor： Erwin Spits

IPC: H02M7/537 ,  H01L27/088

CPC classification number: H03K19/09418 ,  H03K19/09407 ,  H03K19/09445

Abstract: The circuit includes an E-mode transistor with gate-source junction, a D-mode transistor with gate-source junction, a component generating a voltage drop between the source of the D-mode transistor and the drain of the E-mode transistor, and a connection between the drain of the E-mode transistor and the gate of the D-mode transistor. The gate of the E-mode transistor is provided for an input signal, and the drain of the E-mode transistor is provided for an output signal.

Abstract translation: 该电路包括具有栅极 - 源极结的E型晶体管，具有栅极 - 源极结的D型晶体管，在D型晶体管的源极和E型晶体管的漏极之间产生电压降的分量， 以及E型晶体管的漏极与D型晶体管的栅极之间的连接。 E模式晶体管的栅极被提供用于输入信号，并且E模式晶体管的漏极被提供用于输出信号。

公开(公告)号：US20120112793A1

公开(公告)日：2012-05-10

申请号：US13321117

申请日：2010-06-15

Applicant: Erwin Spits ,  Léon C.M. Van den Oever

Inventor： Erwin Spits ,  Léon C.M. Van den Oever

IPC: H03K19/094

CPC classification number: H03K19/09418 ,  H03K19/09407 ,  H03K19/09445

Abstract: A circuit includes E-mode transistors with gate-source junction, a D-mode transistor with gate-source junction. A component generates a voltage drop between the source of the D-mode transistor and the drain of an E-mode transistor provided as a signal output. A connection is made between this drain of the E-mode transistor and the gate of the D-mode transistor, and a signal input at the gates of the E-mode transistors.

Abstract translation: 电路包括具有栅极 - 源极结的E型晶体管，具有栅极 - 源极结的D型晶体管。 组件在D模式晶体管的源极和作为信号输出提供的E模式晶体管的漏极之间产生电压降。 在E模式晶体管的漏极和D模式晶体管的栅极之间进行连接，并在E模式晶体管的栅极处输入信号。