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    Low-Current Logic Plus Driver Circuit
    1.
    发明申请
    Low-Current Logic Plus Driver Circuit 有权
    低电流逻辑加驱动电路

    公开(公告)号：US20120268166A1

    公开(公告)日：2012-10-25

    申请号：US13457244

    申请日：2012-04-26

    Applicant: Léon C.M. van den Oever ,  Erwin Spits

    Inventor： Léon C.M. van den Oever ,  Erwin Spits

    IPC: H03K19/094

    CPC classification number: H03K19/09421 ,  H03K19/09407 ,  H03K19/0952

    Abstract: A circuit includes a logic stage, an inverter stage, and a driver stage. The logic stage and the inverter stage are provided with current limiters, which include a D-mode feedback transistor and a component that generates a voltage drop. A feedback loop connects the source and the gate of the D-mode feedback transistor via this component. The driver stage includes E-mode transistors connected in a totem pole that drive a D-mode transistor and an E-mode transistor to connect and disconnect the load circuit.

    Abstract translation: 电路包括逻辑级，反相器级和驱动级。 逻辑级和反相器级配有限流器，其包括D型反馈晶体管和产生电压降的元件。 反馈环路通过该部件连接D模式反馈晶体管的源极和栅极。 驱动器级包括连接在图腾柱中的E型晶体管，其驱动D模式晶体管和E模式晶体管以连接和断开负载电路。

    Low-Current Input Buffer
    2.
    发明申请
    Low-Current Input Buffer 有权
    低电流输入缓冲器

    公开(公告)号：US20120112801A1

    公开(公告)日：2012-05-10

    申请号：US13322367

    申请日：2010-06-21

    Applicant: Erwin Spits ,  Léon C.M. van den Oever

    Inventor： Erwin Spits ,  Léon C.M. van den Oever

    IPC: H03K3/00 ,  H03K17/687

    CPC classification number: H03K19/018521

    Abstract: A current-limited differential entry stage compares an input signal to a reference voltage generated by a current-limited transistor or diode configuration. Current limiters comprise a D-mode feedback transistor having a gate-source junction. The D-mode transistor is not conducting between the source and the drain if a gate-source voltage is more negative than a negative threshold voltage, and conducting between the source and the drain, otherwise a feedback connection connects the source of the D-mode feedback transistor to its gate via a component that generates a voltage drop.

    Abstract translation: 限流差分输入级将输入信号与由限流晶体管或二极管配置产生的参考电压进行比较。 电流限制器包括具有栅极 - 源极结的D型反馈晶体管。 如果栅源电压比负阈值电压更负，并且在源极和漏极之间导通，则D模式晶体管在源极和漏极之间不导通，否则反馈连接将D模式的源 反馈晶体管通过产生电压降的元件到其栅极。

    BANDGAP REFERENCE CIRCUIT AND METHOD FOR PRODUCING THE CIRCUIT
    3.
    发明申请
    BANDGAP REFERENCE CIRCUIT AND METHOD FOR PRODUCING THE CIRCUIT 有权
    带状参考电路及其制造方法

    公开(公告)号：US20110215789A1

    公开(公告)日：2011-09-08

    申请号：US13039785

    申请日：2011-03-03

    Applicant: Jeroen Bouwman ,  Léon C.M. van den Oever

    Inventor： Jeroen Bouwman ,  Léon C.M. van den Oever

    IPC: G05F3/16

    CPC classification number: G05F3/30

    Abstract: Bandgap reference circuit, comprising a voltage generator (VG) designed to produce a voltage or a current proportional to absolute temperature, a supply circuit (SC), designed to produce a supply for operating the voltage generator (VG), comprising a bias element (BS) and a control element (CS), and a bias circuit (BC), designed to produce a bias for operating the voltage generator (VG), comprising a bias element (BB) and a control element (CB). At least one of the control element (CS) of the supply circuit (SC) and the control element (CB) of the bias circuit (BC) comprises a pseudomorphic high-electron-mobility transistor or a hetero-junction bipolar transistor and/or at least one of the bias element (BS) of the supply circuit (SC) and the bias element (BB) of the bias circuit (BC) comprises a long-gate pseudomorphic high-electron-mobility transistor or a resistor. Method for producing the circuit wherein the pseudomorphic high-electron-mobility transistors and the hetero-junction bipolar transistors are produced using a GaAs BiFET technology process.

    Abstract translation: 带隙参考电路，包括被设计成产生与绝对温度成比例的电压或电流的电压发生器（VG），设计用于产生用于操作电压发生器（VG）的电源的电源电路（SC），包括偏置元件 BS）和控制元件（CS）以及设计成产生用于操作电压发生器（VG）的偏压的偏置电路（BC），包括偏置元件（BB）和控制元件（CB）。 供电电路（SC）的控制元件（CS）和偏置电路（BC）的控制元件（CB）中的至少一个包括伪形高电子迁移率晶体管或异质结双极晶体管和/或 电源电路（SC）的偏置元件（BS）和偏置电路（BC）的偏置元件（BB）中的至少一个包括长栅极伪电容高电子迁移率晶体管或电阻器。 用于制造电路的方法，其中使用GaAs BiFET技术工艺制造假型高电子迁移率晶体管和异质结双极晶体管。

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