Invention Grant
- Patent Title: SiC jfet logic output level-shifting using integrated-series forward-biased jfet gate-to-channel diode junctions
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Application No.: US17229277Application Date: 2021-04-13
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Publication No.: US11838021B1Publication Date: 2023-12-05
- Inventor: Matthew Barlow , James A. Holmes
- Applicant: Matthew Barlow , James A. Holmes
- Applicant Address: US AR Springdale
- Assignee: Matthew Barlow,James A. Holmes
- Current Assignee: Matthew Barlow,James A. Holmes
- Current Assignee Address: US AR Springdale
- Agency: Keisling & Pieper PLC
- Agent David B. Pieper; Trent C. Keisling
- Main IPC: H03K19/094
- IPC: H03K19/094 ; H03K19/09
Abstract:
An improved electrical circuit for logic output level shifting using SiC JFETs with resistors on the input, inverting, stage and using diode degenerated JFET sources in the output stage.
Information query
IPC分类:
