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11.发明公开公开(公告)号：US20240355783A1
公开(公告)日：2024-10-24
申请号：US18757428
申请日：2024-06-27
发明人： Owen R. Fay
IPC分类号： H01L25/065 , H01L21/683 , H01L23/00 , H01L23/498 , H01L23/522 , H01L23/528 , H01L23/532 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/6835 , H01L23/49838 , H01L23/5226 , H01L23/528 , H01L23/53214 , H01L23/53228 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/50 , H01L2221/68359 , H01L2224/11462 , H01L2224/11622 , H01L2224/13022 , H01L2224/13109 , H01L2224/16145 , H01L2224/17181 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565 , H01L2225/06586 , H01L2924/1431 , H01L2924/1434
摘要： Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.
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公开(公告)号：US20240355780A1
公开(公告)日：2024-10-24
申请号：US18387707
申请日：2023-11-07
发明人： Juhyeon KIM , Chajea JO
IPC分类号： H01L25/065 , H01L23/00 , H01L23/31 , H01L23/498 , H01L23/522 , H01L23/528
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/5226 , H01L23/5283 , H01L24/08 , H01L2224/08146 , H01L2924/181
摘要： Semiconductor packages and fabrication methods thereof are provided. A semiconductor package includes first and second structures. The first structure includes: a first semiconductor substrate that has an active surface on which a first semiconductor device is configured to be provided, and an inactive surface opposite to the active surface; a first through via that vertically penetrates the first semiconductor substrate and protrudes from the inactive surface of the first semiconductor substrate; a first protection layer that covers the inactive surface of the first semiconductor substrate and buries the first through via; and a first pad that penetrates at least a portion of the first protection layer and is coupled to the first through via. The second structure includes a second pad, the first structure and the second structure are bonded to each other, and the first pad and the second pad are in contact with each other.
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公开(公告)号：US20240355771A1
公开(公告)日：2024-10-24
申请号：US18305569
申请日：2023-04-24
发明人： Chuei-Tang Wang , Chung-Hao Tsai , Chen-Hua Yu , Wei-Ting Chen , Chia-Chia Lin
IPC分类号： H01L23/00 , H01L23/522
CPC分类号： H01L24/32 , H01L23/5226 , H01L24/73 , H01L2224/32146 , H01L2224/73204
摘要： A method for forming a chip package structure is provided. The method includes providing a first substrate and a second substrate. The first substrate includes a first semiconductor base and a first bonding line over a front surface of the first semiconductor base, and the second substrate includes a second semiconductor base and a second bonding line over the second semiconductor base. The method includes bonding the second substrate to the first substrate. The first bonding line is in contact with the second bonding line. The method includes forming a conductive line over a back surface of the first semiconductor base. The conductive line is thicker than the first bonding line. The method includes forming a conductive bump over the back surface of the first semiconductor base. The conductive line is between the conductive bump and the first semiconductor base.
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公开(公告)号：US20240355745A1
公开(公告)日：2024-10-24
申请号：US18759008
申请日：2024-06-28
申请人： Intel Corporation
发明人： Kemal AYGUN , Zhiguo QIAN , Jianyong XIE
IPC分类号： H01L23/538 , H01L21/48 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/498 , H01L23/522 , H01L23/528 , H01L23/532 , H01L25/065 , H01L25/075 , H01L25/16
CPC分类号： H01L23/5381 , H01L21/4846 , H01L21/486 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/5226 , H01L23/5283 , H01L23/53295 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L25/0753 , H01L25/167 , H01L2224/81 , H01L2924/181
摘要： Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.
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公开(公告)号：US20240355741A1
公开(公告)日：2024-10-24
申请号：US18760444
申请日：2024-07-01
发明人： Shuen-Shin LIANG , Chun-I TSAI , Chih-Wei CHANG , Chun-Hsien HUANG , Hung-Yi HUANG , Keng-Chu LIN , Ken-Yu CHANG , Sung-Li WANG , Chia-Hung CHU , Hsu-Kai CHANG
IPC分类号： H01L23/532 , H01L21/285 , H01L21/768 , H01L23/522
CPC分类号： H01L23/53266 , H01L21/76802 , H01L21/7685 , H01L21/28568 , H01L21/76843 , H01L23/5226
摘要： The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.
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16.发明公开公开(公告)号：US20240355736A1
公开(公告)日：2024-10-24
申请号：US18463266
申请日：2023-09-07
发明人： Chengbao Zhou , Min Wen , Zhen Pan
IPC分类号： H01L23/528 , H01L23/522 , H10B41/20 , H10B41/35 , H10B41/40 , H10B43/20 , H10B43/35 , H10B43/40
CPC分类号： H01L23/5283 , H01L23/5226 , H10B41/20 , H10B41/35 , H10B41/40 , H10B43/20 , H10B43/35 , H10B43/40
摘要： Examples of the present disclosure propose a semiconductor structure and a fabrication method thereof, a memory device, and a memory system. The semiconductor structure includes at least one deck structure. The fabrication method of the deck structure includes: providing a first stack structure in which a peripheral circuit is disposed; forming a first contact and a second contact at least penetrating through the first stack structure; providing a second stack structure in which a memory cell array is disposed; forming a third contact and a fourth contact penetrating through the second stack structure; stacking and bonding the first stack structure and the second stack structure along a first direction to form the deck structure, wherein the first contact is connected with the third contact by bonding to form a first interconnection structure, and the second contact is connected with the fourth contact by bonding to form a second interconnection structure.
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17.发明公开公开(公告)号：US20240355727A1
公开(公告)日：2024-10-24
申请号：US18459894
申请日：2023-09-01
发明人： JAEMYUNG CHOI , Kang -Ill Seo , Se Jung Park
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/76852 , H01L21/76885 , H01L23/53266
摘要： Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a lower metal wire, an upper metal wire on the lower metal wire, a metal via between the lower metal wire and the upper metal wire, the metal via including a lower surface and an upper surface that respectively contact the lower metal wire and the upper metal wire, and a barrier layer extending on a side surface of the metal via. An upper portion of the barrier layer may extend upwardly beyond a lower surface of the upper metal wire.
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18.发明授权公开(公告)号：US12125828B2
公开(公告)日：2024-10-22
申请号：US18464855
申请日：2023-09-11
发明人： Chi-Ching Ho , Bo-Hao Ma , Yu-Ting Xue , Ching-Hung Tseng , Guan-Hua Lu , Hong-Da Chang
IPC分类号： H01L25/065 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/522
CPC分类号： H01L25/0657 , H01L21/486 , H01L21/4882 , H01L21/563 , H01L23/3114 , H01L23/5226 , H01L24/13 , H01L2225/06541
摘要： A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
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公开(公告)号：US12125712B2
公开(公告)日：2024-10-22
申请号：US18227858
申请日：2023-07-28
发明人： Chih-Min Hsiao , Chih-Ming Lai , Chien-Wen Lai , Ya Hui Chang , Ru-Gun Liu
IPC分类号： H01L21/311 , H01L21/768 , H01L23/522 , H01L23/528
CPC分类号： H01L21/31144 , H01L21/76808 , H01L21/76877 , H01L23/5226 , H01L23/528
摘要： A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.
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公开(公告)号：US20240347515A1
公开(公告)日：2024-10-17
申请号：US18757531
申请日：2024-06-28
发明人： Ming-Fa Chen , Sung-Feng Yeh , Tzuan-Horng Liu , Chao-Wen Shih
IPC分类号： H01L25/065 , H01L23/31 , H01L23/522 , H01L23/528 , H01L23/538 , H01L25/00 , H01L21/56 , H01L23/00 , H01L23/29
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/3185 , H01L23/3192 , H01L23/5226 , H01L23/5283 , H01L23/5383 , H01L23/5386 , H01L23/5389 , H01L25/0652 , H01L25/50 , H01L21/561 , H01L23/291 , H01L24/97
摘要： A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer. The second semiconductor chip is embedded within the first semiconductor chip and surrounded by the gap fill layer and the first conductive vias, wherein the second semiconductor chip includes a second semiconductor substrate, a second interconnection layer located on the second semiconductor substrate, a second protection layer located on the second interconnection layer, and second conductive vias embedded in the second protection layer and electrically connected with the second interconnection layer, wherein the second semiconductor substrate is bonded to the first protection layer.
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