公开(公告)号：US5701027A

公开(公告)日：1997-12-23

申请号：US651102

申请日：1996-05-21

Applicant: Kathryn E. Gordon ,  Richard J. Wong

Inventor： Kathryn E. Gordon ,  Richard J. Wong

IPC: H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract translation: 公开了具有抗熔丝的防潮和门阵列，其具有高热稳定性，减小的尺寸，减小的漏电流，在未编程状态下的减小的电容，改进的制造产量和更可控的电特性。 一些反熔丝包括反熔丝通孔中的间隔物。 在一些反熔丝中，可编程材料是平面的，并且顶部或底部电极形成在反熔丝通孔中。 在一些栅极阵列中，反熔丝形成在介电分离两层布线通道之上，而不是在该介电层之下。

公开(公告)号：US5675502A

公开(公告)日：1997-10-07

申请号：US517871

申请日：1995-08-22

Applicant: William Douglas Cox

Inventor： William Douglas Cox

IPC: G06F17/50 ,  G01V3/20

CPC classification number: G06F17/5022

Abstract: Node voltages in a net involving non-linear circuit elements are estimated, successively from one point in time to the next, without a computation-intensive step of solving a set of simultaneous equations. An RC tree representing the net is obtained by modeling circuit elements with resistors, capacitors and voltage sources. Voltages on nodes of the RC tree at a second point in time are then estimated given voltages on the nodes at a previous point in time, by: 1) performing a circuit substitution that enforces a backward stepping rule, and 2) performing a DC analysis thereby obtaining node voltages at the second point in time. In this way, estimated node voltages at successive points in time are obtained by repeating the circuit substitution for the next point in time and by repeating the DC analysis to obtain node voltages at the next point in time. The length of time required for the voltage on a selected node to reach a threshold voltage is the estimated propagation delay.

Abstract translation: 在涉及非线性电路元件的网络中的节点电压从一个时间点到下一个时间点连续地被估计，而不需要求解一组联立方程的计算密集的步骤。 代表网络的RC树通过用电阻，电容和电压源对电路元件进行建模来获得。 然后在第二时间点的RC树的节点上的电压通过以下方式估计在先前时间点上的节点上的电压：1）执行强制反向步进规则的电路替换，以及2）执行DC分析 从而在第二时间点获得节点电压。 以这种方式，通过重复下一个时间点的电路替代，并通过重复DC分析来获得连续时间点的估计节点电压，以便在下一个时间点获得节点电压。 所选节点上的电压达到阈值电压所需的时间长度是估计的传播延迟。

公开(公告)号：US5661412A

公开(公告)日：1997-08-26

申请号：US541662

申请日：1995-10-10

Applicant: Amarpreet S. Chawla ,  Richard J. Wong ,  Andrew K. Chan

Inventor： Amarpreet S. Chawla ,  Richard J. Wong ,  Andrew K. Chan

IPC: G11C17/18 ,  H03K19/177 ,  G11C17/14

CPC classification number: H03K19/17776 ,  G11C17/18 ,  H03K19/17764 ,  H03K19/1778

Abstract: Critical programmed reliability of a metal-to-metal amorphous silicon antifuse is a function of programming current, operating current and total programming time. The time required to program a field programmable gate array is reduced by classifying antifuses to be programmed into three or more classes according to the amount of programming time required to achieve critical programmed reliability under programming current and operating current conditions. Each of these classes of antifuses is programmed with near the minimum programming time required to program every antifuse in the class to critical reliability. In this way, large numbers of antifuses are not programmed with significantly greater amounts of programming time than are actually required to program them to critical reliability. The time required to program the field programmable gate array is therefore reduced. Techniques for obtaining critical reliability data used in classifying antifuses are also disclosed. Classifications based on antifuse type, programming method, and operating conditions are also disclosed.

Abstract translation: 金属对金属非晶硅反熔丝的关键编程可靠性是编程电流，工作电流和总编程时间的函数。 根据在编程电流和工作电流条件下实现关键编程可靠性所需的编程时间量，将减少编程的反熔丝分为三个或更多个等级，从而减少编程现场可编程门阵列所需的时间。 这些类别的反熔丝中的每一个都被编程为将类中的每个反熔丝编程为关键可靠性所需的最小编程时间。 以这种方式，大量的反熔丝不会被编程为比将其编程为关键可靠性所需的显着更大的编程时间。 因此减少了编程现场可编程门阵列所需的时间。 还公开了用于获得用于分类反熔丝的关键可靠性数据的技术。 还公开了基于反熔丝型，编程方法和操作条件的分类。

公开(公告)号：US5587669A

公开(公告)日：1996-12-24

申请号：US399117

申请日：1995-03-03

Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua T. Chua

Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua T. Chua

IPC: H03K19/173 ,  H03K19/177 ,  H03K17/173

CPC classification number: H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17784 ,  H03K19/17792

Abstract: In a field programmable gate array, a plurality of wire segments extend parallel to each other between two logic cells. Some of the wire segments extend to logic cell inputs and others to logic cell outputs. A power wire extends perpendicular to the wire segments and crosses each of the wire segments. Antifuses are disposed to couple the input wire segments to the power wire but no antifuses are disposed between the output wire segments and the power wire.

Abstract translation: 在现场可编程门阵列中，多个线段在两个逻辑单元之间彼此平行延伸。 一些线段延伸到逻辑单元输入，而另一些延伸到逻辑单元输出。 电源线垂直于线段延伸并与每个线段交叉。 防尘装置被布置成将输入线段耦合到电力线，但是在输出线段和电力线之间没有设置反熔丝。

公开(公告)号：US5526276A

公开(公告)日：1996-06-11

申请号：US231595

申请日：1994-04-21

Applicant: William D. Cox ,  Eric E. Lehmann ,  Mukesh T. Lulla ,  Venkatesh R. Nathamuni

Inventor： William D. Cox ,  Eric E. Lehmann ,  Mukesh T. Lulla ,  Venkatesh R. Nathamuni

IPC: G06F17/50 ,  H03K19/177 ,  G06F17/10

CPC classification number: G06F17/5054 ,  H03K19/17704

Abstract: A logic circuit is implemented on a macrocell of a field programmable device using select sets of a logic function which represents a transformation of the one or more input signals of the logic circuit to the output signal of the logic circuit. Select sets of a logic function are determined (i) by grouping input signals which correspond to equal co-factors of the logic function or (ii) by grouping input signals such that one input signal of a group never appears in a term of the logic function in a greedy phase-minimized RMF canonical form without all other input signals of the group. The logic circuit is implemented on a macrocell which includes a circuit element which selects one of two or more input signals according to one or more select signals, each of which is driven by a respective logic gate. Examples of such circuit elements include multiplexers and random access memory (RAM). The logic circuit is implemented by placing on input lines of a logic gate driving a select line the input signals or the complement of the input signals of a select set.

Abstract translation: 逻辑电路在现场可编程器件的宏单元上实现，其使用逻辑功能的选择集合来表示逻辑电路的一个或多个输入信号与逻辑电路的输出信号的变换。 确定逻辑功能的选择集合（i）通过对与逻辑功能的相等协整因子相对应的输入信号进行分组来确定（ii）通过对输入信号进行分组，使得组中的一个输入信号不会出现在逻辑项中 在没有组的所有其他输入信号的情况下，以贪心相位最小化的RMF规范形式运行。 逻辑电路在宏单元上实现，该宏单元包括根据一个或多个选择信号选择两个或更多个输入信号中的一个的电路元件，每个选择信号由相应的逻辑门驱动。 这种电路元件的示例包括多路复用器和随机存取存储器（RAM）。 逻辑电路通过放置在驱动选择线的逻辑门的输入线上来实现选择集的输入信号或输入信号的补码。

公开(公告)号：US5495181A

公开(公告)日：1996-02-27

申请号：US349093

申请日：1994-12-01

Applicant: Paige A. Kolze

Inventor： Paige A. Kolze

IPC: G11C17/18 ,  H03K19/177

CPC classification number: G11C17/18

Abstract: To facilitate the simultaneous programming of multiple antifuses on an integrated circuit, a first current path is established from a first programming terminal (VPP1) of a programmable logic device through a first antifuse to be programmed and a second current path is established from a second programming terminal (VPP2) of the programmable logic device through a second antifuse to be programmed. By supplying the programming current for programming the first antifuse from a different terminal than the programming current for programming the second antifuse, the two antifuses can be programmed simultaneously with an adequate amount of programming current being supplied to each antifuse. A programming current multiplexer circuit is disclosed for selectively coupling either a first programming voltage (VPP1) terminal, a second programming voltage (VPP2), or a ground terminal (GND) to a programming bus and/or to an antifuse to be programmed. The first and second current paths can be established using multiple such programming current multiplexer circuits.

Abstract translation: 为了便于在集成电路上同时对多个反熔丝进行编程，从可编程逻辑器件的第一编程端（VPP1）通过待编程的第一反熔丝建立第一电流路径，并且从第二编程建立第二电流路径 可编程逻辑器件的端子（VPP2）通过要编程的第二反熔丝。 通过提供用于编程来自不同于用于编程第二反熔丝的编程电流的不同端子的第一反熔丝的编程电流，可以在向每个反熔丝提供足够数量的编程电流的同时对两个反熔丝进行编程。 公开了一种编程电流多路复用器电路，用于将第一编程电压（VPP1）端子，第二编程电压（VPP2）或接地端子（GND））选择性地耦合到编程总线和/或将要编程的反熔丝。 可以使用多个这样的编程电流多路复用器电路来建立第一和第二电流路径。

公开(公告)号：US5430390A

公开(公告)日：1995-07-04

申请号：US245309

申请日：1994-05-17

Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

IPC: H03K3/356 ,  H03K17/00 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1778 ,  H03K19/17792

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

公开(公告)号：US5397939A

公开(公告)日：1995-03-14

申请号：US094677

申请日：1993-07-20

Applicant: Kathryn E. Gordon ,  Andrew K. Chan

Inventor： Kathryn E. Gordon ,  Andrew K. Chan

IPC: G11C17/18 ,  H01L21/768 ,  H01L23/525 ,  H03K19/173 ,  G06F7/38

CPC classification number: H01L21/76888 ,  G11C17/18 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: The invention allows programming an antifuse so as to reduce the antifuse resistance and the standard deviation of the resistance without increasing the programming current. This is achieved by passing current pulses of the opposite polarity through the antifuse. In some embodiments, the magnitude of the second pulse is lower than the magnitude of the first pulse. Further, if the antifuse is formed on a semiconductor substrate with one electrode on top of the other electrode and on top of the substrate, the current during the first pulse flows from the top electrode to the bottom electrode and not vice versa. A programming circuitry is provided that allows to program antifuses in a programmable circuit. A driver circuit is connected to each "horizontal" channel and each "vertical" channel. Each driver circuit is controlled by data in the driver circuit. The driver circuits are connected into shift registers so that all the data can be entered from one, two, three or four inputs. No decoding circuitry is necessary. Before programming, the drivers precharge all the channels to an intermediate voltage. During programming, the channels that are not directly connected to the antifuse being programmed are switched to high impedance. As a result, the power consumption is reduced and the programming proceeds faster.

Abstract translation: 本发明允许对反熔丝进行编程，以便在不增加编程电流的情况下降低反熔丝电阻和电阻的标准偏差。 这是通过使相反极性的电流脉冲通过反熔丝来实现的。 在一些实施例中，第二脉冲的幅度低于第一脉冲的幅度。 此外，如果反熔丝形成在半导体衬底上，一个电极在另一个电极的顶部和衬底上，则第一脉冲期间的电流从顶部电极流向底部电极，反之亦然。 提供了一种编程电路，其允许在可编程电路中编程反熔丝。 驱动电路连接到每个“水平”通道和每个“垂直”通道。 每个驱动电路由驱动电路中的数据控制。 驱动器电路连接到移位寄存器，以便所有的数据可以从一个，两个，三个或四个输入输入。 不需要解码电路。 在编程之前，驱动器将所有通道预充电至中间电压。 在编程期间，未直接连接到正在编程的反熔丝的通道切换到高阻抗。 因此，功耗降低，编程进行得更快。

公开(公告)号：US12217811B2

公开(公告)日：2025-02-04

申请号：US18504078

申请日：2023-11-07

Applicant: QuickLogic Corporation

Inventor： Ket Chong Yap ,  Chihhung Liao ,  Shieh Huan Yen

IPC: G11C29/32 ,  G11C29/12 ,  G11C29/20 ,  H03K19/173 ,  H03K19/17728

Abstract: A programmable logic device (PLD) supports scan testing of configurable logical blocks using scannable word line (WL) shift register (WLSR) chains to enable writes to configurable memory bits while scan test data is input via a scan chain comprising scannable bit line (BL) shift registers (BLSRs). Input test data may be shifted onto BLs to write data into a configurable memory bit when a corresponding WL associated with the configurable memory bit is asserted. Logic blocks may comprise: latch-based configurable memory bits, scannable WLSRs forming a distinct WLSR chain in shift mode and driving corresponding WLs. Each WL, when asserted, enables writes to a corresponding configurable memory bit. A scannable BLSR receives serial scan test vector input in shift mode and drives a corresponding BL coupled to the configurable memory bit to write data to the configurable memory bit when the associated WL is asserted.

公开(公告)号：US07646216B2

公开(公告)日：2010-01-12

申请号：US11563632

申请日：2006-11-27

Applicant: Wilma Waiman Shiao ,  Stephen U. Yao ,  Ket-Chong Yap

Inventor： Wilma Waiman Shiao ,  Stephen U. Yao ,  Ket-Chong Yap

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/177 ,  H01L25/00

CPC classification number: H03K19/0008 ,  H03K19/17736 ,  H03K19/17784

Abstract: An apparatus and method of reducing power consumption across a switch, such as an unprogrammed antifuse, is provided. The invention applies to antifuses, other switches such as transistor based switches, (e.g., FLASH, EEPROM and/or SRAM) and other devices exhibiting a leakage current, especially during a sleep or stand-by mode. During a sleep mode, such switches or other devices may be uncoupled from signals driving the switches, then terminals of each switch may be coupled to a common potential or allowed to float to a common potential thereby eliminating or reducing leakage currents through the switches.

Abstract translation: 提供了一种降低开关上的功耗的装置和方法，例如未编程的反熔丝。 本发明适用于反熔丝，诸如基于晶体管的开关的其它开关（例如，FLASH，EEPROM和/或SRAM）以及其它显示泄漏电流的器件，特别是在睡眠或待机模式期间。 在睡眠模式期间，这样的开关或其他装置可以与驱动开关的信号分离，然后每个开关的端子可以耦合到公共电位或允许浮动到公共电位，从而消除或减少通过开关的漏电流。