公开(公告)号：US5416367A

公开(公告)日：1995-05-16

申请号：US189352

申请日：1994-01-31

Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua T. Chua ,  William D. Cox

Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua T. Chua ,  William D. Cox

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17784 ,  H03K19/17792

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a plurality of logic cells ("modules") integrated with the programmable configuration network. Each logic cell is a powerful general purpose universal logic building block. Each logic cell consists essentially of four two-input AND gates, one or two six-input AND gates, three multiplexers, and a D-type flipflop.

Abstract translation: 现场可编程门阵列包括可编程路由网络，与可编程路由网络集成的可编程配置网络; 以及与可编程配置网络集成的多个逻辑单元（“模块”）。 每个逻辑单元都是一个功能强大的通用逻辑构建块。 每个逻辑单元基本上由四个双输入与门，一个或两个六输入与门，三个多路复用器和D型触发器组成。

公开(公告)号：US5587669A

公开(公告)日：1996-12-24

申请号：US399117

申请日：1995-03-03

Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua T. Chua

Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua T. Chua

IPC: H03K19/173 ,  H03K19/177 ,  H03K17/173

CPC classification number: H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17784 ,  H03K19/17792

Abstract: In a field programmable gate array, a plurality of wire segments extend parallel to each other between two logic cells. Some of the wire segments extend to logic cell inputs and others to logic cell outputs. A power wire extends perpendicular to the wire segments and crosses each of the wire segments. Antifuses are disposed to couple the input wire segments to the power wire but no antifuses are disposed between the output wire segments and the power wire.

Abstract translation: 在现场可编程门阵列中，多个线段在两个逻辑单元之间彼此平行延伸。 一些线段延伸到逻辑单元输入，而另一些延伸到逻辑单元输出。 电源线垂直于线段延伸并与每个线段交叉。 防尘装置被布置成将输入线段耦合到电力线，但是在输出线段和电力线之间没有设置反熔丝。

公开(公告)号：US5726586A

公开(公告)日：1998-03-10

申请号：US744225

申请日：1996-11-05

Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

IPC: H03K3/356 ,  H03K17/00 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1778 ,  H03K19/17792

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

公开(公告)号：US5502315A

公开(公告)日：1996-03-26

申请号：US161504

申请日：1993-12-02

Applicant: Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner ,  Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas

Inventor： Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner ,  Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas

IPC: H01L23/525 ,  H02L27/02

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

Abstract translation: 在形成具有显着降低的漏电流的非晶硅反熔丝的一种方法中，在两个电极之间的反熔丝通孔中形成非晶硅膜。 非晶硅膜使用等离子体增强化学气相沉积，优选在硅烷 - 氩气环境中并在200-500℃的温度下沉积，或者以各种反应性气体反应溅射。 在另一种方法中，将氧化物层放置在两个非晶硅膜层之间。 在另一种方法中，围绕氧化物层的非晶硅膜之一被掺杂。 在另一个实施例中，在非晶硅膜上或下形成导电的，高度可扩散的材料层。 选择非晶硅膜的特征尺寸和厚度，以在提供期望的编程电压的同时进一步最小化漏电流。 还描述了用于形成具有反熔丝的现场可编程门阵列的方法。

公开(公告)号：US6078191A

公开(公告)日：2000-06-20

申请号：US38728

申请日：1998-03-10

Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

IPC: H03K3/356 ,  H03K17/00 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1778 ,  H03K19/17792

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract translation: 现场可编程门阵列包括可编程路由网络，与可编程路由网络集成的可编程配置网络; 以及与可编程配置网络集成的逻辑单元。 逻辑单元包括四个双输入与门，两个六输入与门，三个多路复用器和延迟触发器。 逻辑单元是一种强大的通用逻辑构建块，适用于实现大多数TTL和门阵列宏图程序功能。 相当多种功能可以通过一个单元延迟来实现，包括宽达十三个输入的组合逻辑功能，最多三个输入的所有布尔传递函数，以及顺序触发器功能，如T，JK和带进位的计数。

公开(公告)号：US5989943A

公开(公告)日：1999-11-23

申请号：US447969

申请日：1989-12-08

Applicant: Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas ,  Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner

Inventor： Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas ,  Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner

IPC: H01L21/82 ,  H01L23/525 ,  H01L27/10 ,  H01L21/28

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

公开(公告)号：US5122685A

公开(公告)日：1992-06-16

申请号：US665103

申请日：1991-03-06

Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

IPC: H03K3/356 ,  H03K17/00 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1778 ,  H03K19/17792

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract translation: 现场可编程门阵列包括可编程路由网络，与可编程路由网络集成的可编程配置网络; 以及与可编程配置网络集成的逻辑单元。 逻辑单元包括四个双输入与门，两个六输入与门，三个多路复用器和延迟触发器。 逻辑单元是一种强大的通用逻辑构建块，适用于实现大多数TTL和门阵列宏图程序功能。 相当多种功能可以通过一个单元延迟来实现，包括宽达十三个输入的组合逻辑功能，最多三个输入的所有布尔传递函数，以及顺序触发器功能，如T，JK和带进位的计数。

公开(公告)号：US6150199A

公开(公告)日：2000-11-21

申请号：US405979

申请日：1999-09-27

Applicant: Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas ,  Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner

Inventor： Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas ,  Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner

IPC: H01L21/82 ,  H01L23/525 ,  H01L27/10

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

Abstract translation: 在形成具有显着降低的漏电流的非晶硅反熔丝的一种方法中，在两个电极之间的反熔丝通孔中形成非晶硅膜。 非晶硅膜使用等离子体增强化学气相沉积，优选在硅烷 - 氩气环境中并在200-500℃的温度下沉积，或者以各种反应性气体反应溅射。 在另一种方法中，将氧化物层放置在两个非晶硅膜层之间。 在另一种方法中，围绕氧化物层的非晶硅膜之一被掺杂。 在另一个实施例中，在非晶硅膜上或下形成导电的，高度可扩散的材料层。 选择非晶硅膜的特征尺寸和厚度，以在提供期望的编程电压的同时进一步最小化漏电流。 还描述了用于形成具有反熔丝的现场可编程门阵列的方法。

公开(公告)号：US5780919A

公开(公告)日：1998-07-14

申请号：US646823

申请日：1996-05-21

Applicant: Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner ,  Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas

Inventor： Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner ,  Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas

IPC: H01L21/82 ,  H01L23/525 ,  H01L27/10 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for forming a field programmable gate array with antifuses.

Abstract translation: 在形成具有显着降低的漏电流的非晶硅反熔丝的一种方法中，在两个电极之间的反熔丝通孔中形成非晶硅膜。 非晶硅膜使用等离子体增强化学气相沉积，优选在硅烷 - 氩气环境中并在200-500℃的温度下沉积，或者以各种反应性气体反应溅射。 在另一种方法中，将氧化物层放置在两个非晶硅膜层之间。 在另一种方法中，围绕氧化物层的非晶硅膜之一被掺杂。 在另一个实施例中，在非晶硅膜上或下形成导电的，高度可扩散的材料层。 选择非晶硅膜的特征尺寸和厚度，以在提供期望的编程电压的同时进一步最小化漏电流。 描述了用反熔丝形成现场可编程门阵列的方法。

公开(公告)号：US5717230A

公开(公告)日：1998-02-10

申请号：US323168

申请日：1994-10-13

Applicant: Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner ,  Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas

Inventor： Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner ,  Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas

IPC: H01L23/525 ,  H01L27/02

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: A field programmable gate array has a programmable interconnect structure comprising metal signal conductors and metal-to-metal PECVD amorphous silicon antifuses. The metal-to-metal PECVD amorphous silicon antifuses have an unprogrammed resistance of at least 550 megaohms and a programmed resistance of under 200 ohms.

Abstract translation: 现场可编程门阵列具有包括金属信号导体和金属对金属PECVD非晶硅反熔丝的可编程互连结构。 金属对金属PECVD非晶硅反熔丝具有至少550兆欧姆的未编程电阻和低于200欧姆的编程电阻。