公开(公告)号：US5471154A

公开(公告)日：1995-11-28

申请号：US372611

申请日：1995-01-13

Applicant: Kathryn E. Gordon ,  Andrew K. Chan

Inventor： Kathryn E. Gordon ,  Andrew K. Chan

IPC: G11C17/18 ,  H01L21/768 ,  H01L23/525 ,  H03K19/173 ,  G06F7/38

CPC classification number: H01L21/76888 ,  G11C17/18 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: The invention allows programming an antifuse so as to reduce the antifuse resistance and the standard deviation of the resistance without increasing the programming current. This is achieved by passing current pulses of the opposite polarity through the antifuse. In some embodiments, the magnitude of the second pulse is lower than the magnitude of the first pulse. Further, if the antifuse is formed on a semiconductor substrate with one electrode on top of the other electrode and on top of the substrate, the current during the first pulse flows from the top electrode to the bottom electrode and not vice versa. A programming circuitry is provided that allows to program antifuses in a programmable circuit. A driver circuit is connected to each "horizontal" channel and each "vertical" channel. Each driver circuit is controlled by data in the driver circuit. The driver circuits are connected into shift registers so that all the data can be entered from one, two, three or four inputs. No decoding circuitry is necessary. Before programming, the drivers precharge all the channels to an intermediate voltage. During programming, the channels that are not directly connected to the antifuse being programmed are switched to high impedance. As a result, the power consumption is reduced and the programming proceeds faster.

公开(公告)号：US5302546A

公开(公告)日：1994-04-12

申请号：US738707

申请日：1991-07-31

Applicant: Kathryn E. Gordon ,  Andrew K. Chan

Inventor： Kathryn E. Gordon ,  Andrew K. Chan

IPC: G11C17/18 ,  H01L21/768 ,  H01L23/525 ,  H01L21/14 ,  H01L21/306

CPC classification number: H01L21/76888 ,  G11C17/18 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: The invention allows programming an antifuse so as to reduce the antifuse resistance and the standard deviation of the resistance without increasing the programming current. This is achieved by passing current pulses of the opposite polarity through the antifuse. In some embodiments, the magnitude of the second pulse is lower than the magnitude of the first pulse. Further, if the antifuse is formed on a semiconductor substrate with one electrode on top of the other electrode and on top of the substrate, the current during the first pulse flows from the top electrode to the bottom electrode and not vice versa. A programming circuitry is provided that allows to program antifuses in a programmable circuit. A driver circuit is connected to each "horizontal" channel and each "vertical" channel. Each driver circuit is controlled by data in the driver circuit. The driver circuits are connected into shift registers so that all the data can be entered from one, two, three or four inputs. No decoding circuitry is necessary. Before programming, the drivers precharge all the channels to an intermediate voltage. During programming, the channels that are not directly connected to the antifuse being programmed are switched to high impedance. As a result, the power consumption is reduced and the programming proceeds faster.

Abstract translation: 本发明允许对反熔丝进行编程，以便在不增加编程电流的情况下降低反熔丝电阻和电阻的标准偏差。 这是通过使相反极性的电流脉冲通过反熔丝来实现的。 在一些实施例中，第二脉冲的幅度低于第一脉冲的幅度。 此外，如果反熔丝形成在半导体衬底上，一个电极在另一个电极的顶部和衬底上，则第一脉冲期间的电流从顶部电极流向底部电极，反之亦然。 提供了一种编程电路，其允许在可编程电路中编程反熔丝。 驱动电路连接到每个“水平”通道和每个“垂直”通道。 每个驱动电路由驱动电路中的数据控制。 驱动器电路连接到移位寄存器，以便所有的数据可以从一个，两个，三个或四个输入输入。 不需要解码电路。 在编程之前，驱动器将所有通道预充电至中间电压。 在编程期间，未直接连接到正在编程的反熔丝的通道切换到高阻抗。 因此，功耗降低，编程进行得更快。

公开(公告)号：US5397939A

公开(公告)日：1995-03-14

申请号：US094677

申请日：1993-07-20

Applicant: Kathryn E. Gordon ,  Andrew K. Chan

Inventor： Kathryn E. Gordon ,  Andrew K. Chan

IPC: G11C17/18 ,  H01L21/768 ,  H01L23/525 ,  H03K19/173 ,  G06F7/38

CPC classification number: H01L21/76888 ,  G11C17/18 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: The invention allows programming an antifuse so as to reduce the antifuse resistance and the standard deviation of the resistance without increasing the programming current. This is achieved by passing current pulses of the opposite polarity through the antifuse. In some embodiments, the magnitude of the second pulse is lower than the magnitude of the first pulse. Further, if the antifuse is formed on a semiconductor substrate with one electrode on top of the other electrode and on top of the substrate, the current during the first pulse flows from the top electrode to the bottom electrode and not vice versa. A programming circuitry is provided that allows to program antifuses in a programmable circuit. A driver circuit is connected to each "horizontal" channel and each "vertical" channel. Each driver circuit is controlled by data in the driver circuit. The driver circuits are connected into shift registers so that all the data can be entered from one, two, three or four inputs. No decoding circuitry is necessary. Before programming, the drivers precharge all the channels to an intermediate voltage. During programming, the channels that are not directly connected to the antifuse being programmed are switched to high impedance. As a result, the power consumption is reduced and the programming proceeds faster.

Abstract translation: 本发明允许对反熔丝进行编程，以便在不增加编程电流的情况下降低反熔丝电阻和电阻的标准偏差。 这是通过使相反极性的电流脉冲通过反熔丝来实现的。 在一些实施例中，第二脉冲的幅度低于第一脉冲的幅度。 此外，如果反熔丝形成在半导体衬底上，一个电极在另一个电极的顶部和衬底上，则第一脉冲期间的电流从顶部电极流向底部电极，反之亦然。 提供了一种编程电路，其允许在可编程电路中编程反熔丝。 驱动电路连接到每个“水平”通道和每个“垂直”通道。 每个驱动电路由驱动电路中的数据控制。 驱动器电路连接到移位寄存器，以便所有的数据可以从一个，两个，三个或四个输入输入。 不需要解码电路。 在编程之前，驱动器将所有通道预充电至中间电压。 在编程期间，未直接连接到正在编程的反熔丝的通道切换到高阻抗。 因此，功耗降低，编程进行得更快。

公开(公告)号：US6154054A

公开(公告)日：2000-11-28

申请号：US309165

申请日：1999-05-10

Applicant: Mehul D. Shroff ,  Rajiv Jain ,  Andre Stolmeijer ,  Kathryn E. Gordon

Inventor： Mehul D. Shroff ,  Rajiv Jain ,  Andre Stolmeijer ,  Kathryn E. Gordon

IPC: H01L23/525 ,  H03K19/177

CPC classification number: H01L23/5252 ,  H01L23/525 ,  H01L2924/0002

Abstract: A field programmable gate array has antifuses disposed over logic modules. Each of these antifuses includes a conductive plug and an overlaying region of programmable material (for example, amorphous silicon). To program one of these antifuses, an electric connection is formed through the programmable material to couple the conductive plug to a metal conductor that overlays the region of programmable material. The metal conductor includes a layer of a barrier metal to separate another metal of the conductor (for example, aluminum from an aluminum layer) from migrating into the programmable material when the antifuse is unprogrammed. In some embodiments, less than three percent of all antifuses of the field programmable gate array has a corner (from the top-down perspective) of the region of programmable material that is disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse. In some embodiments, less than seventy-five percent of all antifuses of the field programmable gate array have an edge of the region of programmable material disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse. Other antifuse structures and methods are also disclosed for preventing programmable material corners and/or edges from compromising yield and/or reliability of programmable devices.

Abstract translation: 现场可编程门阵列具有置于逻辑模块上的反熔丝。 这些反熔丝中的每一个包括导电插塞和可编程材料（例如，非晶硅）的覆盖区域。 为了编程这些反熔丝之一，通过可编程材料形成电连接，以将导电插塞耦合到覆盖可编程材料区域的金属导体。 当反熔丝未编程时，金属导体包括隔离金属层，以将导体的另一金属（例如铝从铝层分离）迁移到可编程材料中。 在一些实施例中，现场可编程门阵列的所有反熔丝的小于3％具有可编程材料区域（在导电插塞的横向距离DIS内）（在金属的下侧视角内）的拐角（在导电插塞的横向距离DIS内） 该反熔丝的导体。 在一些实施例中，现场可编程门阵列的所有反熔丝的小于百分之七十五的边缘都是在该反熔丝的金属导体之下设置（在导电插塞的横向距离DIS内）的可编程材料区域的边缘。 还公开了其他反熔丝结构和方法，用于防止可编程材料拐角和/或边缘损害可编程器件的产量和/或可靠性。

公开(公告)号：US5319238A

公开(公告)日：1994-06-07

申请号：US920734

申请日：1992-07-28

Applicant: Kathryn E. Gordon ,  Richard J. Wong

Inventor： Kathryn E. Gordon ,  Richard J. Wong

IPC: H01L21/768 ,  H01L23/525 ,  H01L27/02 ,  H01L23/48 ,  H01L29/34 ,  H01L29/46

CPC classification number: H01L23/5252 ,  H01L21/76888 ,  H01L2924/0002

Abstract: An amorphous silicon antifuse has a bottom electrode, a dielectric overlying the bottom electrode, amorphous silicon contacting the bottom electrode in a via in the dielectric, and the top electrode over the amorphous silicon. Spacers are provided in the via corners between the amorphous silicon and the top electrode. The spacers smooth the surface above the amorphous silicon, provide good top electrode step coverage, and reduce leakage current. Another amorphous silicon antifuse is provided in which the amorphous silicon layer is planar. The planarity makes the amorphous silicon layer easy to manufacture. A programmable CMOS circuit is provided in which the antifuses are formed over the intermetal dielectric. The antifuses are not affected by the high temperatures associated with the formation of the intermetal dielectric and the first-metal contacts. The intermetal dielectric protects the circuit elements during the antifuse formation. The bottom electrodes of the antifuses are connected to the first-metal contacts. The overall capacitance associated with the antifuses is low, and hence the circuit is fast.

公开(公告)号：US5196724A

公开(公告)日：1993-03-23

申请号：US874983

申请日：1992-04-23

Applicant: Kathryn E. Gordon ,  Richard J. Wong

Inventor： Kathryn E. Gordon ,  Richard J. Wong

IPC: H01L21/768 ,  H01L23/525

CPC classification number: H01L23/5252 ,  H01L21/76888 ,  H01L2924/0002

Abstract: An amorphous silicon antifuse has a bottom electrode, a dielectric overlying the bottom electrode, amorphous silicon contacting the bottom electrode in a via in the dielectric, and the top electrode over the amorphous silicon. Spacers are provided in the via corners between the amorphous silicon and the top electrode. The spacers smooth the surface above the amorphous silicon, provide good top electrode step coverage, and reduce leakage current. Another amorphous silicon antifuse is provided in which the amorphous silicon layer is planar. The planarity makes the amorphous silicon layer easy to manufacture. A programmable CMOS circuit is provided in which the antifuse are formed over the intermetal dielectric. The antifuse are not affected by the high temperatures associated with the formation of the intermetal dielectric and the first-metal contacts. The intermetal dielectric protects the circuit elements during the antifuse formation. The bottom electrodes of the antifuses are connected to the first-metal contacts. The overall capacitance associated with the antifuses is low, and hence the circuit is fast.

Abstract translation: 非晶硅反熔丝具有底部电极，覆盖底部电极的电介质，与电介质中的通孔中的底部电极接触的非晶硅以及非晶硅上的顶部电极。 隔板设置在非晶硅和顶部电极之间的通孔拐角处。 间隔物平滑无定形硅上方的表面，提供良好的顶部电极台阶覆盖，并减少漏电流。 提供另一种非晶硅反熔丝，其中非晶硅层是平面的。 平面度使得非晶硅层容易制造。 提供了可编程CMOS电路，其中反熔丝形成在金属间电介质上。 反熔丝不受与金属间电介质和第一金属触点的形成相关的高温的影响。 金属间介质在反熔丝形成期间保护电路元件。 反熔丝的底部电极连接到第一金属触点。 与反熔丝相关的总电容低，因此电路快。

公开(公告)号：US5955751A

公开(公告)日：1999-09-21

申请号：US133999

申请日：1998-08-13

Applicant: Mehul D. Shroff ,  Rajiv Jain ,  Andre Stolmeijer ,  Kathryn E. Gordon

Inventor： Mehul D. Shroff ,  Rajiv Jain ,  Andre Stolmeijer ,  Kathryn E. Gordon

IPC: H01L23/525 ,  H01L23/52 ,  H01L23/528

CPC classification number: H01L23/5252 ,  H01L23/525 ,  H01L2924/0002

Abstract: A field programmable gate array has antifuses disposed over logic modules. Each of these antifuses includes a conductive plug and an overlaying region of programmable material (for example, amorphous silicon). To program one of these antifuses, an electric connection is formed through the programmable material to couple the conductive plug to a metal conductor that overlays the region of programmable material. The metal conductor includes a layer of a barrier metal to separate another metal of the conductor (for example, aluminum from an aluminum layer) from migrating into the programmable material when the antifuse is unprogrammed. In some embodiments, less than three percent of all antifuses of the field programmable gate array has a corner (from the top-down perspective) of the region of programmable material that is disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse. In some embodiments, less than seventy-five percent of all antifuses of the field programmable gate array have an edge of the region of programmable material disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse. Other antifuse structures and methods are also disclosed for preventing programmable material corners and/or edges from compromising yield and/or reliability of programmable devices.

公开(公告)号：US5557136A

公开(公告)日：1996-09-17

申请号：US892466

申请日：1992-06-01

Applicant: Kathryn E. Gordon ,  Richard J. Wong

Inventor： Kathryn E. Gordon ,  Richard J. Wong

IPC: H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

公开(公告)号：US5544070A

公开(公告)日：1996-08-06

申请号：US937331

申请日：1992-08-27

Applicant: William D. Cox ,  Andrew K. L. Chan ,  Richard J. Wong ,  James M. Apland ,  Kathryn E. Gordon

Inventor： William D. Cox ,  Andrew K. L. Chan ,  Richard J. Wong ,  James M. Apland ,  Kathryn E. Gordon

IPC: G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H03K19/177

CPC classification number: H03K19/17764 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H03K19/17704 ,  H03K19/1778 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: A programmable device comprises a first antifuse programmed with a first programming method and a second antifuse programmed with a second programming method, whereby an actual operating current flowing through the second antifuse exceeds a maximum permissible operating current of the first antifuse but does not exceed a maximum permissible operating current of the second antifuse, whereby an actual operating current flowing through the first antifuse does not exceed the maximum permissible operating current of the first antifuse, and whereby an actual operating current flowing through the second antifuse does not exceed the maximum permissible operating current of the second antifuse. By allowing the use of a programming method on some antifuses which would not be adequate for the programming of other antifuses, the realization of user-specific circuits in field programmable devices is facilitated and the reliability of user-specific circuits realized in field programmable devices is enhanced.

Abstract translation: 可编程器件包括用第一编程方法编程的第一反熔丝和用第二编程方法编程的第二反熔丝，由此流过第二反熔丝的实际工作电流超过第一反熔丝的最大允许工作电流但不超过最大值 第二反熔丝的允许工作电流，由此流过第一反熔丝的实际工作电流不超过第一反熔丝的最大允许工作电流，由此流过第二反熔丝的实际工作电流不超过最大允许工作电流 的第二个反熔丝。 通过允许在一些反熔丝上使用编程方法来编程其他抗反熔丝，对于现场可编程器件中的用户特定电路的实现是有利的，并且在现场可编程器件中实现的用户特定电路的可靠性是 增强。

公开(公告)号：US6097077A

公开(公告)日：2000-08-01

申请号：US75493

申请日：1998-05-08

Applicant: Kathryn E. Gordon ,  Richard J. Wong

Inventor： Kathryn E. Gordon ,  Richard J. Wong

IPC: H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract translation: 公开了具有抗熔丝的防潮和门阵列，其具有高的热稳定性，减小的尺寸，减小的漏电流，在未编程状态下的减小的电容，改善的制造产量和更可控的电特性。 一些反熔丝包括反熔丝通孔中的间隔物。 在一些反熔丝中，可编程材料是平面的，并且顶部或底部电极形成在反熔丝通孔中。 在一些栅极阵列中，反熔丝形成在介电分离两层布线通道之上，而不是在该介电层之下。