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    Programmable logic device with design for test functionality
    1.
    发明授权
    Programmable logic device with design for test functionality 有权

    公开(公告)号：US12217811B2

    公开(公告)日：2025-02-04

    申请号：US18504078

    申请日：2023-11-07

    Applicant: QuickLogic Corporation

    Inventor： Ket Chong Yap ,  Chihhung Liao ,  Shieh Huan Yen

    IPC: G11C29/32 ,  G11C29/12 ,  G11C29/20 ,  H03K19/173 ,  H03K19/17728

    Abstract: A programmable logic device (PLD) supports scan testing of configurable logical blocks using scannable word line (WL) shift register (WLSR) chains to enable writes to configurable memory bits while scan test data is input via a scan chain comprising scannable bit line (BL) shift registers (BLSRs). Input test data may be shifted onto BLs to write data into a configurable memory bit when a corresponding WL associated with the configurable memory bit is asserted. Logic blocks may comprise: latch-based configurable memory bits, scannable WLSRs forming a distinct WLSR chain in shift mode and driving corresponding WLs. Each WL, when asserted, enables writes to a corresponding configurable memory bit. A scannable BLSR receives serial scan test vector input in shift mode and drives a corresponding BL coupled to the configurable memory bit to write data to the configurable memory bit when the associated WL is asserted.

    CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE
    2.
    发明公开
    CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE 审中-公开

    公开(公告)号：US20240171178A1

    公开(公告)日：2024-05-23

    申请号：US18504072

    申请日：2023-11-07

    Applicant: QuickLogic Corporation

    Inventor： Ket Chong Yap ,  Chihhung Liao

    IPC: H03K19/1776 ,  G11C11/419 ,  H03K19/20

    CPC classification number: H03K19/1776 ,  G11C11/419 ,  H03K19/20

    Abstract: An area efficient readable and resettable configuration memory latch is disclosed that maintains latch data integrity through read and write operations and includes a non-terminated inout bit line (BL). During write operations, enabled by a Word Line Write (WLW) signal, the non-terminated inout BL drives data to be written, while, during read operations, enabled by a Word Line Read (WLR) signal, the state of the BL is indicative of a data stored in the latch. A pull-down network is activated when the WLR signal is asserted and the stored data is logic one and, when activated, operates to pull down the BL to logic zero; the pull-down network is inactive otherwise. A weak pull-up operates to pull up the BL when the pull-down network is inactive. A sensing block is configured to sense the state of the BL when the WLR signal and a read enable signal are both asserted.

    Area-efficient configuration latch for programmable logic device
    4.
    发明授权
    Area-efficient configuration latch for programmable logic device 有权

    公开(公告)号：US11935618B2

    公开(公告)日：2024-03-19

    申请号：US17725564

    申请日：2022-04-21

    Applicant: QuickLogic Corporation

    Inventor： Ket Chong Yap ,  Chihhung Liao ,  Shieh Huan Yen

    IPC: G11C7/00 ,  G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  H03K19/017

    CPC classification number: G11C7/1039 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/08 ,  H03K19/01742

    Abstract: An area efficient input terminated readable and resettable configuration memory latch is disclosed. A pull-up network and a pair of pull-down networks operate to set the value of an internal node based, in part, on the state of the input terminated bit line and a word line write input. The internal node is inverted to form the output of the configuration memory latch. A reset line operates to reset the latch and a reset cycle is initiated prior to each write cycle. In some embodiments, the configuration memory latch includes a scan mode input, which, when asserted, facilitates automated testing of a programmable logic device that includes the configuration memory latch. Asserting the scan mode input enables Design for Test functionality. A sensing block is configured to sense the state of the bit when a word line read signal and a read enable signal are both asserted.

    Sectional configuration for programmable logic devices
    5.
    发明授权
    Sectional configuration for programmable logic devices 有权

    公开(公告)号：US11652486B1

    公开(公告)日：2023-05-16

    申请号：US17697862

    申请日：2022-03-17

    Applicant: QuickLogic Corporation

    Inventor： Ket Chong Yap ,  Chihhung Liao

    IPC: H03K19/1776 ,  H03K19/17704 ,  H03K19/17736

    CPC classification number: H03K19/1776 ,  H03K19/1774 ,  H03K19/17708 ,  H03K19/17744

    Abstract: A bit line (BL) may be coupled at a first end to a BL driver (BLD) and at a second end to a BL receiver (BLR). The BL include a plurality of sections and each BL section may be coupled to at least one corresponding sectional configuration memory latch controlled by: at least one sectional word line write (WLW-k) signal, which when asserted enables data to be written into the at least one corresponding sectional configuration memory latch when a corresponding tri-stateable sectional driver (SD-k) is activated, and at least one sectional word line read (WLR-k) signal, which when asserted enables data to be from the at least one corresponding sectional configuration memory latch when the corresponding sectional pull-up (PU-k) is activated.

    Configuration latch for programmable logic device
    6.
    发明授权
    Configuration latch for programmable logic device 有权

    公开(公告)号：US11848671B2

    公开(公告)日：2023-12-19

    申请号：US17697856

    申请日：2022-03-17

    Applicant: QuickLogic Corporation

    Inventor： Ket Chong Yap ,  Chihhung Liao

    IPC: G11C11/419 ,  H03K19/1776 ,  H03K19/20

    CPC classification number: H03K19/1776 ,  G11C11/419 ,  H03K19/20

    Abstract: An area efficient readable and resettable configuration memory latch is disclosed that maintains latch data integrity through read and write operations and includes a non-terminated inout bit line (BL). During write operations, enabled by a Word Line Write (WLW) signal, the non-terminated inout BL drives data to be written, while, during read operations, enabled by a Word Line Read (WLR) signal, the state of the BL is indicative of a data stored in the latch. A pull-down network is activated when the WLR signal is asserted and the stored data is logic one and, when activated, operates to pull down the BL to logic zero; the pull-down network is inactive otherwise. A weak pull-up operates to pull up the BL when the pull-down network is inactive. A sensing block is configured to sense the state of the BL when the WLR signal and a read enable signal are both asserted.

    AREA-EFFICIENT CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE
    7.
    发明公开
    AREA-EFFICIENT CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE 审中-公开

    公开(公告)号：US20230343372A1

    公开(公告)日：2023-10-26

    申请号：US17725564

    申请日：2022-04-21

    Applicant: QuickLogic Corporation

    Inventor： Ket Chong Yap ,  Chihhung Liao ,  Shieh Huan Yen

    IPC: G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  H03K19/017

    CPC classification number: G11C7/1039 ,  G11C7/1096 ,  G11C7/1069 ,  G11C7/12 ,  G11C8/08 ,  H03K19/01742

    Abstract: An area efficient input terminated readable and resettable configuration memory latch is disclosed. A pull-up network and a pair of pull-down networks operate to set the value of an internal node based, in part, on the state of the input terminated bit line and a word line write input. The internal node is inverted to form the output of the configuration memory latch. A reset line operates to reset the latch and a reset cycle is initiated prior to each write cycle. In some embodiments, the configuration memory latch includes a scan mode input, which, when asserted, facilitates automated testing of a programmable logic device that includes the configuration memory latch. Asserting the scan mode input enables Design for Test functionality. A sensing block is configured to sense the state of the bit when a word line read signal and a read enable signal are both asserted.

    Configuration latch for programmable logic device
    8.
    发明授权
    Configuration latch for programmable logic device 有权

    公开(公告)号：US12149244B2

    公开(公告)日：2024-11-19

    申请号：US18504072

    申请日：2023-11-07

    Applicant: QuickLogic Corporation

    Inventor： Ket Chong Yap ,  Chihhung Liao

    IPC: G11C11/419 ,  H03K19/1776 ,  H03K19/20

    Abstract: An area efficient readable and resettable configuration memory latch maintains latch data integrity through read and write operations and includes a non-terminated inout bit line (BL). During write operations, enabled by a Word Line Write (WLW) signal, the non-terminated inout BL drives data to be written, while, during read operations, enabled by a Word Line Read (WLR) signal, the state of the BL is indicative of a data stored in the latch. A pull-down network is activated when the WLR signal is asserted and the stored data is logic one and, when activated, operates to pull down the BL to logic zero; the pull-down network is inactive otherwise. A weak pull-up operates to pull up the BL when the pull-down network is inactive. A sensing block is configured to sense the state of the BL when the WLR signal and a read enable signal are both asserted.

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