Invention Publication
- Patent Title: PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY
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Application No.: US18504078Application Date: 2023-11-07
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Publication No.: US20240170087A1Publication Date: 2024-05-23
- Inventor: Ket Chong Yap , Chihhung Liao , Shieh Huan Yen
- Applicant: QuickLogic Corporation
- Applicant Address: US CA San Jose
- Assignee: QuickLogic Corporation
- Current Assignee: QuickLogic Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G11C29/32
- IPC: G11C29/32 ; G11C29/12 ; G11C29/20 ; H03K19/173 ; H03K19/17728

Abstract:
A programmable logic device (PLD) supports scan testing of configurable logical blocks using scannable word line (WL) shift register (WLSR) chains to enable writes to configurable memory bits while scan test data is input via a scan chain comprising scannable bit line (BL) shift registers (BLSRs). Input test data may be shifted onto BLs to write data into a configurable memory bit when a corresponding WL associated with the configurable memory bit is asserted. Logic blocks may comprise: latch-based configurable memory bits, scannable WLSRs forming a distinct WLSR chain in shift mode and driving corresponding WLs. Each WL, when asserted, enables writes to a corresponding configurable memory bit. A scannable BLSR receives serial scan test vector input in shift mode and drives a corresponding BL coupled to the configurable memory bit to write data to the configurable memory bit when the associated WL is asserted.
Public/Granted literature
- US12217811B2 Programmable logic device with design for test functionality Public/Granted day:2025-02-04
Information query
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