公开(公告)号：US5526276A

公开(公告)日：1996-06-11

申请号：US231595

申请日：1994-04-21

Applicant: William D. Cox ,  Eric E. Lehmann ,  Mukesh T. Lulla ,  Venkatesh R. Nathamuni

Inventor： William D. Cox ,  Eric E. Lehmann ,  Mukesh T. Lulla ,  Venkatesh R. Nathamuni

IPC: G06F17/50 ,  H03K19/177 ,  G06F17/10

CPC classification number: G06F17/5054 ,  H03K19/17704

Abstract: A logic circuit is implemented on a macrocell of a field programmable device using select sets of a logic function which represents a transformation of the one or more input signals of the logic circuit to the output signal of the logic circuit. Select sets of a logic function are determined (i) by grouping input signals which correspond to equal co-factors of the logic function or (ii) by grouping input signals such that one input signal of a group never appears in a term of the logic function in a greedy phase-minimized RMF canonical form without all other input signals of the group. The logic circuit is implemented on a macrocell which includes a circuit element which selects one of two or more input signals according to one or more select signals, each of which is driven by a respective logic gate. Examples of such circuit elements include multiplexers and random access memory (RAM). The logic circuit is implemented by placing on input lines of a logic gate driving a select line the input signals or the complement of the input signals of a select set.

Abstract translation: 逻辑电路在现场可编程器件的宏单元上实现，其使用逻辑功能的选择集合来表示逻辑电路的一个或多个输入信号与逻辑电路的输出信号的变换。 确定逻辑功能的选择集合（i）通过对与逻辑功能的相等协整因子相对应的输入信号进行分组来确定（ii）通过对输入信号进行分组，使得组中的一个输入信号不会出现在逻辑项中 在没有组的所有其他输入信号的情况下，以贪心相位最小化的RMF规范形式运行。 逻辑电路在宏单元上实现，该宏单元包括根据一个或多个选择信号选择两个或更多个输入信号中的一个的电路元件，每个选择信号由相应的逻辑门驱动。 这种电路元件的示例包括多路复用器和随机存取存储器（RAM）。 逻辑电路通过放置在驱动选择线的逻辑门的输入线上来实现选择集的输入信号或输入信号的补码。