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    LATENCY CONTROL IN A TRANSMITTER/RECEIVER BUFFER
    11.
    发明申请
    LATENCY CONTROL IN A TRANSMITTER/RECEIVER BUFFER 有权
    发射机/接收机缓存器中的延迟控制

    公开(公告)号：US20160164665A1

    公开(公告)日：2016-06-09

    申请号：US14561452

    申请日：2014-12-05

    Applicant: Xilinx, Inc.

    Inventor： David F. Taylor ,  Matthew H. Klein ,  Vincent Vendramini

    IPC: H04L7/033 ,  H03L7/06 ,  H04L12/861 ,  H03H11/20

    CPC classification number: H04L49/90 ,  G06F5/06 ,  G06F5/10 ,  G06F5/12 ,  G06F2205/126 ,  H03L7/06 ,  H03L7/07 ,  H03M9/00

    Abstract: In a method for buffering, a buffer buffers data responsive to read and write clock signals. A flag signal from the buffer is for a fill level thereof. The flag signal is toggled responsive to the data buffered being either above or below a set point for the fill level. A phase of the write clock signal is adjusted to a phase of the read clock signal responsive to the toggling of the flag signal. The write clock signal is used to control latency of the buffer. The adjusting of the phase of the write clock signal includes: generating an override signal responsive to the toggling of the flag signal; and inputting the read clock signal and the override signal to a phase adjuster to controllably adjust the phase of the write clock signal to the phase of the read clock signal during operation.

    Abstract translation: 在缓冲方法中，缓冲器缓冲响应于读和写时钟信号的数据。 来自缓冲器的标志信号用于其填充水平。 响应于缓冲的数据高于或低于填充水平的设定点，该标志信号被切换。 响应于标志信号的切换，写时钟信号的相位被调整为读时钟信号的相位。 写时钟信号用于控制缓冲器的延迟。 写时钟信号的相位的调整包括：响应于标志信号的切换产生超控信号; 并将读取的时钟信号和超控信号输入到相位调节器，以在操作期间将写时钟信号的相位可控地调节到读时钟信号的相位。

    Methods of making integrated circuit products
    12.
    发明授权
    Methods of making integrated circuit products 有权
    制作集成电路产品的方法

    公开(公告)号：US09012245B1

    公开(公告)日：2015-04-21

    申请号：US14493078

    申请日：2014-09-22

    Applicant: Xilinx, Inc.

    Inventor： Matthew H. Klein ,  Robert W. Wells ,  Jongheon Jeong

    IPC: H01L21/44 ,  H01L21/66

    CPC classification number: H01L22/20 ,  H01L22/14 ,  H01L22/22 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/15311

    Abstract: In the disclosed methods, integrated circuit (IC) dice are manufactured from a common specification, and the IC dice are tested for defective circuitry. Respective defect sets are generated to indicate defective circuitry in the IC die. The dice are assigned to bins based on the respective defect sets. For each bin, all IC dice assigned to the bin have equivalent respective defect sets. Product definitions are provided, and each product definition indicates a respective set of circuitry required for a corresponding product. Respective sets of packages are manufactured for each product. In the manufacturing of each package of a respective set of packages for each product, one or more IC dice are selected from a subset of the plurality of bins such that the IC dice have respective defect sets allowed by the product definition of the product. The selected IC dice are then manufactured into the package.

    Abstract translation: 在所公开的方法中，集成电路（IC）芯片由公共规范制造，IC芯片被测试有缺陷的电路。 产生各个缺陷组以指示IC芯片中的有缺陷的电路。 基于相应的缺陷集，将骰子分配给箱子。 对于每个仓，分配给仓的所有IC骰子都具有相应的各自的缺陷集。 提供了产品定义，每个产品定义都表示相应产品所需的相应电路组。 为每个产品制造各套包装。 在针对每个产品的相应的一组包装的每个包装的制造中，从多个箱的子集中选择一个或多个IC骰子，使得IC骰子具有由产品的产品定义允许的各自的缺陷组。 然后将选定的IC芯片制造成封装。

    Method for determining critical junction temperature
    14.
    发明授权
    Method for determining critical junction temperature 有权
    确定关键结温的方法

    公开(公告)号：US08694939B1

    公开(公告)日：2014-04-08

    申请号：US13802181

    申请日：2013-03-13

    Applicant: Xilinx, Inc.

    Inventor： Alan M. Frost ,  Matthew H. Klein ,  Ronald L. Cline

    IPC: G06F17/50

    CPC classification number: G06F17/5054 ,  G06F2217/84

    Abstract: A method for determining a critical junction temperature for a user-design implemented in a field programmable gate array (programmable device), includes: obtaining a static power vs. temperature curve for the user-design implemented in the programmable device; obtaining a system thermal curve for the user-design implemented in the programmable device; and using the static power vs. temperature curve for the user-design implemented in the programmable device and the system thermal curve for the user-design implemented in the programmable device to determine the critical junction temperature.

    Abstract translation: 用于确定在现场可编程门阵列（可编程器件）中实现的用户设计的关键结温度的方法包括：获得在可编程器件中实现的用户设计的静态功率对温度曲线; 获得在可编程设备中实现的用户设计的系统热曲线; 并使用在可编程器件中实现的用户设计的静态功率与温度曲线以及在可编程器件中实现的用户设计的系统热曲线来确定临界结温度。

    MULTI-CHIP STRUCTURE INCLUDING A MEMORY DIE STACKED ON DIE HAVING PROGRAMMABLE INTEGRATED CIRCUIT
    15.
    发明申请
    MULTI-CHIP STRUCTURE INCLUDING A MEMORY DIE STACKED ON DIE HAVING PROGRAMMABLE INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20200343234A1

    公开(公告)日：2020-10-29

    申请号：US16392170

    申请日：2019-04-23

    Applicant: Xilinx, Inc.

    Inventor： Matthew H. Klein

    IPC: H01L25/18 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

    Abstract: Some examples described herein provide for a multi-chip structure including one or more memory dies stacked on a die having a programmable integrated circuit (IC). In an example, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable IC, and the programmable IC includes a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

    DATABASE LOOKUP USING A SCANNABLE CODE FOR PART SELECTION
    16.
    发明申请
    DATABASE LOOKUP USING A SCANNABLE CODE FOR PART SELECTION 审中-公开

    公开(公告)号：US20190122282A1

    公开(公告)日：2019-04-25

    申请号：US15793332

    申请日：2017-10-25

    Applicant: Xilinx, Inc.

    Inventor： Matthew H. Klein ,  Wei Yee Jocelyn Teo ,  Craig E. Taylor

    IPC: G06Q30/06 ,  G06K7/10 ,  G06F17/30 ,  G06F21/30

    Abstract: Embodiments described herein include techniques for providing information regarding a hardware part using a scannable code so that a customer can make an informed decision when placing the hardware part in a larger computing system. A customer may purchase hardware parts that are categorized into a certain bin which has guaranteed range of power consumption or performance. The customer may over design the computing system to accommodate the worst parameter in the range (e.g., the minimum performance or the maximum power consumption) to ensure the timing or power specifications are not violated. Instead, the embodiments herein provide a scannable code on the hardware part which the customer can use to access a database which stores more granular information about the part. The customer can use the performance parameters to make better informed decisions to determine where to place the part in the computing system.

    Estimating power consumption of a circuit design
    18.
    发明授权
    Estimating power consumption of a circuit design 有权
    估计电路设计的功耗

    公开(公告)号：US09268898B1

    公开(公告)日：2016-02-23

    申请号：US13797810

    申请日：2013-03-12

    Applicant: Xilinx, Inc.

    Inventor： Alan M. Frost ,  Matthew H. Klein

    IPC: G06F17/50

    CPC classification number: G06F17/5036 ,  G06F2217/78

    Abstract: Estimating power consumption of a circuit design includes associating, using a processor, each partition of a plurality of partitions of a circuit design with a probability distribution (315). For each partition, the associated probability distribution specifies a distribution for a probability distribution parameter correlated with power consumption for the partition. Using the processor, an output probability distribution specifying power consumption of the circuit design can be calculated according to the probability distribution of each partition of the circuit design (320).

    Abstract translation: 估计电路设计的功耗包括使用处理器将电路设计的多个分区的每个分区与概率分布相关联（315）。 对于每个分区，相关联的概率分布指定与分区的功耗相关的概率分布参数的分布。 使用处理器，可以根据电路设计的每个分区的概率分布来计算指定电路设计的功耗的输出概率分布（320）。

    Method and apparatus for single event upset (SEU) detection and correction
    19.
    发明授权
    Method and apparatus for single event upset (SEU) detection and correction 有权
    单次事件不适（SEU）检测和校正的方法和装置

    公开(公告)号：US08635581B1

    公开(公告)日：2014-01-21

    申请号：US13842502

    申请日：2013-03-15

    Applicant: Xilinx, Inc.

    Inventor： Chen W. Tseng ,  Weiguang Lu ,  Karthy Rajasekharan ,  Matthew H. Klein ,  Restu I. Ismail

    IPC: G06F11/22 ,  G06F17/50

    CPC classification number: G06F11/263 ,  G06F2217/14

    Abstract: A method, non-transitory computer readable medium, and apparatus for performing single event upset detection and correction are disclosed. For example, the method comprises: setting, by a processor, at least one starting address for each of a plurality of rows of a design for an integrated circuit, setting, by the processor, at least one ending address for each of the plurality of rows of the design, and performing, by the processor, the single event upset detection and correction scan in parallel, from the at least one starting address for each of the plurality of rows to the at least one ending address for each of the plurality of rows.

    Abstract translation: 公开了一种用于执行单事件不正常检测和校正的方法，非暂时性计算机可读介质和装置。 例如，该方法包括：由处理器设置用于集成电路的设计的多行中的每一行的至少一个起始地址，由处理器设置用于多个集合电路中的每一个的至少一个结束地址 并且由处理器并行执行单个事件镦锻检测和校正扫描，从多个行中的每个行的至少一个起始地址到多个行中的每一个的至少一个结束地址 行。

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