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公开(公告)号：US20180287837A1
公开(公告)日：2018-10-04
申请号：US15471364
申请日：2017-03-28
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Yohan Frans , Geoffrey Zhang
CPC classification number: H04L27/01 , H03M1/182 , H03M1/361 , H04B1/06 , H04B2203/5425 , H04L25/063 , H04Q2213/03
Abstract: A receiver includes: an automatic gain controller (AGC) configured to receive an analog signal; an analog-to-digital converter (ADC) configured to receive an output from the AGC and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data, and a least significant bit of the digitized signal corresponds to an error signal; and an adaptation unit configured to control the AGC, the ADC, or both the AGC and the ADC, based at least in part on the digitized signal to achieve a desired data digitization and data slicing.
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公开(公告)号：US09806915B1
公开(公告)日：2017-10-31
申请号：US15194302
申请日：2016-06-27
Applicant: Xilinx, Inc.
Inventor： Mohamed N. Elzeftawi , Hongtao Zhang
CPC classification number: H04L25/03019 , H03B5/06 , H03B5/366 , H03B2200/005 , H03B2200/0062 , H03G3/3036 , H04B1/10 , H04L25/03885
Abstract: A continuous time linear equalizer comprises an input of a first equalizer path configured to receive a first differential input signal; an input of a second equalizer path configured to receive a second differential input signal; a first programmable load capacitor coupled to an output of the first equalizer path; a second programmable load capacitor coupled to an output of the second equalizer path; and a programmable source capacitor coupled between the first equalizer path and the second equalizer path.
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公开(公告)号：US09276782B1
公开(公告)日：2016-03-01
申请号：US14698588
申请日：2015-04-28
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Geoffrey Zhang , Yu Liao
IPC: H04L25/03
CPC classification number: H04L25/03146 , H04L25/03057
Abstract: In a receiver, there is a precursor iterative canceller (“PIC”) having first and second paths. A postcursor decision block is coupled to the PIC to provide a decision signal thereto. The PIC includes: comparators for receiving an input signal and corresponding threshold inputs for precursor ISI speculation; and select circuits for selecting a first speculative input for the first path and a second speculative input for the second path, respectively associated with a negative precursor contribution and a positive precursor contribution. The first path and the second path in combination include at least a first stage and a second stage for processing the first speculative input and the second speculative input. The decision signal is provided to the first stage and to the select circuits. The select circuits are coupled to receive the decision signal for selection of the first speculative input and the second speculative input.
Abstract translation: 在接收机中，存在具有第一和第二路径的前体迭代消除器（“PIC”）。 后端决策块被耦合到PIC以向其提供判决信号。 PIC包括：用于接收输入信号的比较器和用于前体ISI投机的相应阈值输入; 以及选择用于选择第一路径的第一推测输入和用于第二路径的第二推测输入，分别与负前驱贡献和正前驱贡献相关联。 组合的第一路径和第二路径包括用于处理第一推测输入和第二推测输入的至少第一级和第二级。 决定信号被提供给第一级和选择电路。 选择电路被耦合以接收用于选择第一推测输入和第二推测输入的判定信号。
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公开(公告)号：US12063129B2
公开(公告)日：2024-08-13
申请号：US17665477
申请日：2022-02-04
Applicant: XILINX, INC.
Inventor： Hongtao Zhang , Winson Lin , Arianne Roldan , Yohan Frans , Geoff Zhang
CPC classification number: H04L25/03057 , H03L7/0891 , H04L27/01 , H04L2025/0349
Abstract: An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.
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公开(公告)号：US11855652B2
公开(公告)日：2023-12-26
申请号：US17643349
申请日：2021-12-08
Applicant: XILINX, INC.
Inventor： Hao-Wei Hung , Tan Kee Hian , Siok Wei Lim , Hongtao Zhang
CPC classification number: H03M1/1023 , H03M1/1047 , H03M9/00 , H03M1/66
Abstract: A multiplexer (MUX) calibration system includes main MUX circuitry, first replica MUX circuitry, digital-to-analog (DAC) circuitry, detection circuitry, and control circuitry. The main MUX circuitry receives clock signals and outputs a first data signal based on the clock signals. The first replica MUX circuitry receives the clock signals and outputs a second data signal based on the clock signals. The DAC circuitry generates an offset voltage. The detection circuitry receives the second data signal and the offset voltage and generates a first error signal based on one or more of the second data signal and the offset voltage. The control circuitry receives the first error signal and generates a first control signal indicating an adjustment to the clock signals.
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Patent Agency Ranking
公开(公告)号：US10742453B1
公开(公告)日：2020-08-11
申请号：US16283453
申请日：2019-02-22
Applicant: Xilinx, Inc.
Inventor： Min Wu , Hongtao Zhang , Yu Xu
IPC: H04L25/03
Abstract: An equalizer circuit including a filter, equalization circuitry, and a filter adaptation circuit. The filter is configured to produce a linearized signal based at least in part on a received input signal and a nonlinear transfer function. The equalization circuitry is configured to filter inter-symbol interference (ISI) and detect one or more data symbols in the linearized signal. The equalization circuitry is further configured to produce an error signal indicating an amount of error in the detected data symbols. The filter adaptation circuit is configured to dynamically adjust the nonlinear transfer function of the filter based at least in part on the error signal from the equalization circuitry.
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公开(公告)号：US09882795B1
公开(公告)日：2018-01-30
申请号：US14689327
申请日：2015-04-17
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Geoffrey Zhang , Yu Xu , Patrick Satarzadeh , Zhaoyin D. Wu
CPC classification number: H04L43/0811 , H04L7/0087 , H04L25/03057
Abstract: In an example, an apparatus for detecting signal loss on a serial communication channel coupled to a receiver includes an input, a detector, and an output circuit. The input is configured to receive decisions generated by sampling the serial communication channel using multiplexed decision paths in a decision feedback equalizer (DFE). The detector is coupled to the input and configured to monitor the decisions for at least one pattern generated by the multiplexed decision paths in response to absence of a serial data signal on the serial communication channel. The output circuit is coupled to the detector and configured to assert loss-of-signal in response detection of the at least one pattern by the detector.
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公开(公告)号：US09800438B1
公开(公告)日：2017-10-24
申请号：US15333505
申请日：2016-10-25
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Zhaoyin D. Wu , Christopher J. Borrelli , Geoffrey Zhang
CPC classification number: H04L25/03885 , G01R31/02 , G01R31/44 , H04L7/0025 , H04L7/0087 , H04L25/03273
Abstract: An example method of performing an eye-scan in a receiver includes: generating digital samples from an analog signal input to the receiver based on a sampling clock, the sampling clock phase-shifted with respect to a reference clock based on a phase interpolator (PI) code; equalizing the digital samples based on first equalization parameters of a plurality of equalization parameters of the receiver; adapting the plurality of equalization parameters and performing clock recovery based on the digital samples to generate the PI code; and performing a plurality of cycles of locking the plurality of equalization parameters, suspending phase detection in the clock recovery, offsetting the PI code, collecting an output of the receiver, resuming the phase detection in the clock recovery, and unlocking the equalization parameters to perform the eye scan.
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公开(公告)号：US09654327B2
公开(公告)日：2017-05-16
申请号：US14723171
申请日：2015-05-27
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Geoffrey Zhang , Hongtao Zhang , Kun-Yung Chang , Toan Pham , Zhaoyin D. Wu
CPC classification number: H04L27/3809 , H04L25/03057 , H04L25/03885
Abstract: A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.
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20.发明授权公开(公告)号：US09379920B1
公开(公告)日：2016-06-28
申请号：US14707919
申请日：2015-05-08
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Hongtao Zhang , Kun-Yung Chang , Geoffrey Zhang
CPC classification number: H04L25/03057 , H04L25/03 , H04L25/03146 , H04L25/03878 , H04L25/03885 , H04L27/01 , H04L2025/0349 , H04L2025/03503
Abstract: In a receiver, a decision feedback equalizer (“DFE”) receives an analog input signal. The DFE includes a subtraction block for subtracting weighted postcursor decisions from an analog input signal to provide an analog output signal. A postcursor decision block coupled to the DFE compares the analog output signal against positive and negative values of a postcursor coefficient to provide first and second possible decisions for selecting a current postcursor-based decision therebetween responsive to a previous postcursor-based decision. A precursor cancellation block receives the analog output signal, the previous postcursor-based decision and the current postcursor-based decision for providing a digital output signal for a previous sample of the analog input signal.
Abstract translation: 在接收机中，判决反馈均衡器（“DFE”）接收模拟输入信号。 DFE包括用于从模拟输入信号减去加权后移判定的减法模块以提供模拟输出信号。 耦合到DFE的后端判定块将模拟输出信号与后移系数的正值和负值进行比较，以响应于先前的基于后期的判定来提供用于选择当前基于后台的判定的第一和第二可能决定。 前体消除块接收模拟输出信号，先前的基于后期的判定和当前的基于前后的判定，用于为模拟输入信号的先前样本提供数字输出信号。
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