公开(公告)号：US11949425B2

公开(公告)日：2024-04-02

申请号：US17669254

申请日：2022-02-10

Applicant: XILINX, INC.

Inventor： Kai-An Hsieh ,  Tan Kee Hian

IPC: H03M1/08 ,  H03M1/76 ,  H04L25/02

CPC classification number: H03M1/0863 ,  H03M1/765 ,  H04L25/0272 ,  H04L25/0278

Abstract: A digital-to-analog converter (DAC)-based voltage-mode transmit driver architecture. One example transmit driver circuit generally includes an impedance control circuit coupled to a plurality of DAC driver slices. The impedance control circuit generally includes a tunable impedance configured to be adjusted to match a load impedance for the transmit driver circuit. Another example transmit driver circuit generally has an output impedance that is smaller than the load impedance for the transmit driver circuit, such that an output voltage swing at differential output nodes of the transmit driver circuit is greater than a voltage of a power supply rail. Another example transmit driver circuit generally includes a predriver circuit with a first inverter coupled to a first output of the predriver circuit and a second inverter coupled to a second output of the predriver circuit, the transistors in at least one of the first inverter or the second inverter having different strengths.

公开(公告)号：US11482993B1

公开(公告)日：2022-10-25

申请号：US17183176

申请日：2021-02-23

Applicant: XILINX, INC.

Inventor： Kai-An Hsieh ,  Tan Kee Hian

IPC: H03K5/24 ,  H03H7/38 ,  H03H7/06

Abstract: Embodiments herein describe placing a filter network at one of the inputs of the comparator to avoid injecting unequal amounts of kickback noise into the inputs of the comparator. In one embodiment, the filter network matches the impedance seen at the inputs of the comparator. As a result, the amount of kickback noise is essentially equal at the inputs even though the input signals may be at different frequencies. Thus, the kickback noise is essentially cancelled out so that this noise has little to no impact on the output of the comparator.

公开(公告)号：US11855652B2

公开(公告)日：2023-12-26

申请号：US17643349

申请日：2021-12-08

Applicant: XILINX, INC.

Inventor： Hao-Wei Hung ,  Tan Kee Hian ,  Siok Wei Lim ,  Hongtao Zhang

IPC: H03M1/10 ,  H03M9/00 ,  H03M1/66

CPC classification number: H03M1/1023 ,  H03M1/1047 ,  H03M9/00 ,  H03M1/66

Abstract: A multiplexer (MUX) calibration system includes main MUX circuitry, first replica MUX circuitry, digital-to-analog (DAC) circuitry, detection circuitry, and control circuitry. The main MUX circuitry receives clock signals and outputs a first data signal based on the clock signals. The first replica MUX circuitry receives the clock signals and outputs a second data signal based on the clock signals. The DAC circuitry generates an offset voltage. The detection circuitry receives the second data signal and the offset voltage and generates a first error signal based on one or more of the second data signal and the offset voltage. The control circuitry receives the first error signal and generates a first control signal indicating an adjustment to the clock signals.

公开(公告)号：US11764797B2

公开(公告)日：2023-09-19

申请号：US17449293

申请日：2021-09-29

Applicant: XILINX, INC.

Inventor： Kai-An Hsieh ,  Tan Kee Hian ,  Kevin Zheng

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/0607 ,  H03M1/00 ,  H03M1/06 ,  H03M1/10 ,  H03M1/12

Abstract: Analog-to-digital converter circuitry includes comparator circuitry, capacitor analog-to-digital converter circuitry (CDA), and successive approximation register (SAR) circuitry. The comparator circuitry includes a non-inverting input and an inverting input to selectively receive a differential voltage signal, and an output. The CDAC circuitry includes a first capacitor network having a first plurality of capacitors. A first capacitor of the first plurality of capacitors includes a first terminal connected to the non-inverting input and a second terminal selectively connected to a first voltage potential and a second voltage potential. The first voltage potential is greater than the second voltage potential. The SAR circuitry is connected to the output and the first capacitor network, and connects, during a first period, the second terminal of the first capacitor to the second voltage potential. The non-inverting input and the inverting input are connected to the differential voltage signal during the first period.