Phase-locked loop with an adjustable output divider
    1.
    发明授权
    Phase-locked loop with an adjustable output divider 有权
    带有可调输出分频器的锁相环

    公开(公告)号:US09385769B2

    公开(公告)日:2016-07-05

    申请号:US14562531

    申请日:2014-12-05

    Applicant: Xilinx, Inc.

    Abstract: An apparatus relates generally to providing a divided signal output. In such an apparatus, a controller is coupled to receive a reference frequency count and a feedback frequency count to determine a difference therebetween to provide a control setting. A divider is coupled to receive the control setting to provide the divided signal output. The divider includes an adjustable load impedance. The control setting is coupled to adjust the load impedance of the divider to adjust a self-resonance frequency of the divider.

    Abstract translation: 一种装置一般涉及提供分频信号输出。 在这种装置中,控制器被耦合以接收参考频率计数和反馈频率计数,以确定它们之间的差异以提供控制设置。 耦合分频器以接收控制设置以提供分频信号输出。 分压器包括可调负载阻抗。 控制设置被耦合以调整分频器的负载阻抗,以调整分频器的自谐振频率。

    Fractional-N PLL-based CDR with a low-frequency reference
    3.
    发明授权
    Fractional-N PLL-based CDR with a low-frequency reference 有权
    基于分数N的基于PLL的CDR具有低频参考

    公开(公告)号:US09306730B1

    公开(公告)日:2016-04-05

    申请号:US14613652

    申请日:2015-02-04

    Applicant: Xilinx, Inc.

    Abstract: An apparatus relates generally to clock and data recovery. A fractional-N phase-locked loop is for receiving a reference signal, and for providing a proportional signal and an integral signal. A ring oscillator of the fractional-N phase-locked loop is for receiving the proportional signal and the integral signal, and for providing an oscillation signal at a clock frequency substantially greater than a reference frequency of the reference signal. A data-to-frequency control word converter is for receiving data input and the oscillation signal, and for providing a frequency control word. A fractional-N divider of the fractional-N phase-locked loop is for receiving the frequency control word and the oscillation signal, and for providing a feedback clock signal to a phase-frequency detector of the fractional-N phase-locked loop. The phase-frequency detector is for receiving the reference signal and the feedback clock signal, and for adjusting a phase and frequency of the oscillation signal.

    Abstract translation: 一种装置一般涉及时钟和数据恢复。 小数N锁相环用于接收参考信号,并用于提供比例信号和积分信号。 分数N锁相环的环形振荡器用于接收比例信号和积分信号,并用于以基本上大于参考信号的参考频率的时钟频率提供振荡信号。 数据到频率控制字转换器用于接收数据输入和振荡信号,并用于提供频率控制字。 分数N锁相环的分数N分频器用于接收频率控制字和振荡信号,并将反馈时钟信号提供给分数N锁相环的相位检波器。 相位检测器用于接收参考信号和反馈时钟信号,并用于调整振荡信号的相位和频率。

    PHASE-LOCKED LOOP WITH AN ADJUSTABLE OUTPUT DIVIDER
    5.
    发明申请
    PHASE-LOCKED LOOP WITH AN ADJUSTABLE OUTPUT DIVIDER 有权
    具有可调输出分路器的相位锁定环路

    公开(公告)号:US20160164558A1

    公开(公告)日:2016-06-09

    申请号:US14562531

    申请日:2014-12-05

    Applicant: XILINX, INC.

    Abstract: An apparatus relates generally to providing a divided signal output. In such an apparatus, a controller is coupled to receive a reference frequency count and a feedback frequency count to determine a difference therebetween to provide a control setting. A divider is coupled to receive the control setting to provide the divided signal output. The divider includes an adjustable load impedance. The control setting is coupled to adjust the load impedance of the divider to adjust a self-resonance frequency of the divider.

    Abstract translation: 一种装置一般涉及提供分频信号输出。 在这种装置中,控制器被耦合以接收参考频率计数和反馈频率计数,以确定它们之间的差异以提供控制设置。 耦合分频器以接收控制设置以提供分频信号输出。 分压器包括可调负载阻抗。 控制设置被耦合以调整分频器的负载阻抗,以调整分频器的自谐振频率。

    Fractional-N multiplying injection-locked oscillation
    6.
    发明授权
    Fractional-N multiplying injection-locked oscillation 有权
    小数N乘以注入锁定振荡

    公开(公告)号:US09306585B1

    公开(公告)日:2016-04-05

    申请号:US14613648

    申请日:2015-02-04

    Applicant: Xilinx, Inc.

    Abstract: An apparatus relates generally to the generation of an oscillating signal. In this apparatus, a fractional-N generator is for receiving a frequency control word and a reference signal. A multiplying injection-locked oscillator is coupled to the fractional-N generator for receiving a clock signal for outputting an oscillating signal. A frequency tracking loop is coupled to the fractional-N generator for receiving the clock signal, and further coupled to the multiplying injection-locked oscillator for receiving the oscillating signal.

    Abstract translation: 装置一般涉及振荡信号的产生。 在该装置中,分数N发生器用于接收频率控制字和参考信号。 倍增注入锁定振荡器耦合到分数N发生器,用于接收用于输出振荡信号的时钟信号。 频率跟踪环耦合到分数N发生器用于接收时钟信号,并且还耦合到乘法注入锁定振荡器以接收振荡信号。

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