Fractional-N PLL-based CDR with a low-frequency reference
    1.
    发明授权
    Fractional-N PLL-based CDR with a low-frequency reference 有权
    基于分数N的基于PLL的CDR具有低频参考

    公开(公告)号:US09306730B1

    公开(公告)日:2016-04-05

    申请号:US14613652

    申请日:2015-02-04

    Applicant: Xilinx, Inc.

    Abstract: An apparatus relates generally to clock and data recovery. A fractional-N phase-locked loop is for receiving a reference signal, and for providing a proportional signal and an integral signal. A ring oscillator of the fractional-N phase-locked loop is for receiving the proportional signal and the integral signal, and for providing an oscillation signal at a clock frequency substantially greater than a reference frequency of the reference signal. A data-to-frequency control word converter is for receiving data input and the oscillation signal, and for providing a frequency control word. A fractional-N divider of the fractional-N phase-locked loop is for receiving the frequency control word and the oscillation signal, and for providing a feedback clock signal to a phase-frequency detector of the fractional-N phase-locked loop. The phase-frequency detector is for receiving the reference signal and the feedback clock signal, and for adjusting a phase and frequency of the oscillation signal.

    Abstract translation: 一种装置一般涉及时钟和数据恢复。 小数N锁相环用于接收参考信号,并用于提供比例信号和积分信号。 分数N锁相环的环形振荡器用于接收比例信号和积分信号,并用于以基本上大于参考信号的参考频率的时钟频率提供振荡信号。 数据到频率控制字转换器用于接收数据输入和振荡信号,并用于提供频率控制字。 分数N锁相环的分数N分频器用于接收频率控制字和振荡信号,并将反馈时钟信号提供给分数N锁相环的相位检波器。 相位检测器用于接收参考信号和反馈时钟信号,并用于调整振荡信号的相位和频率。

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