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公开(公告)号：US11769710B2
公开(公告)日：2023-09-26
申请号：US16833034
申请日：2020-03-27
申请人： XILINX, INC.
发明人： Gamal Refai-Ahmed , Suresh Ramalingam , Ken Chang , Mayank Raj , Chuan Xie , Yohan Frans
IPC分类号： H01L23/473 , H01L25/16 , H01L23/367 , H01L23/40
CPC分类号： H01L23/473 , H01L23/3675 , H01L25/167 , H01L2023/4062
摘要： Some examples described herein provide for a heterogeneous integration module (HIM) that includes a thermal management apparatus. In an example, an apparatus (e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second component. The thermal management apparatus has a first thermal energy flow path for dissipating thermal energy generated by the first component and has a second thermal energy flow path for dissipating thermal energy generated by the second component. The first thermal energy flow path has a lower thermal resistivity than the second thermal energy flow path.
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公开(公告)号：US10749532B1
公开(公告)日：2020-08-18
申请号：US16291286
申请日：2019-03-04
申请人： Xilinx, Inc.
摘要： A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO), a first loop circuit, and a second loop circuit. The first loop circuit includes a first loop filter configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The second loop circuit includes a compensation circuit configured to receive a reference signal and the first signal, and provide a second VCO frequency control signal to the VCO.
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公开(公告)号：US20190207687A1
公开(公告)日：2019-07-04
申请号：US15862058
申请日：2018-01-04
申请人： Xilinx, Inc.
发明人： Mayank Raj
IPC分类号： H04B17/18 , H04B10/516
CPC分类号： H04B17/18 , H04B10/516
摘要： An optical driver is disclosed, including a PMOS pull-up circuit, an NMOS pull-down circuit, and an inductive circuit. The PMOS pull-up circuit may include a first terminal to receive a first input signal based on a received data signal, and a P output terminal coupled to the inductive circuit. The NMOS pull-down circuit may include a second input terminal to receive a second input signal based on the received data signal, and an N output terminal coupled to the inductive circuit. The inductive circuit may include an L output terminal to output an output signal, a P coil coupled between the P output terminal and the L output terminal, and an N coil coupled between the N output terminal and the L output terminal. The P coil may be configured to hide a parasitic capacitance associated with the PMOS pull-up circuit during a falling edge transition of the received data signal, and the N coil may be configured to hide a parasitic capacitance associated with the NMOS pull-down circuit during a rising edge transition of the received data signal.
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公开(公告)号：US10014868B1
公开(公告)日：2018-07-03
申请号：US15476861
申请日：2017-03-31
申请人： Xilinx, Inc.
发明人： Mayank Raj
CPC分类号： H03L7/24 , H04L7/0025 , H04L7/033 , H04L7/0337
摘要： An example phase interpolator includes: a ring oscillator having a plurality of delay stages and a plurality of injection switches, each of the plurality of injection switches responsive to a differential reference clock signal and a first differential control signal; a supply control circuit configured to provide a regulated supply voltage to the ring oscillator in response to a first component of a second differential control signal; and a ground control circuit configured to provide a regulated ground voltage to the ring oscillator in response to a second component of the second differential control signal.
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公开(公告)号：US09742380B1
公开(公告)日：2017-08-22
申请号：US15170797
申请日：2016-06-01
申请人： Xilinx, Inc.
发明人： Mayank Raj , Parag Upadhyaya , Adebabay M. Bekele
IPC分类号： H03L7/06 , H03K3/013 , H03K5/04 , H03K7/08 , H03L7/18 , H03L7/197 , H03L7/093 , H03L7/091 , H03L7/089
CPC分类号： H03K3/013 , H03K5/04 , H03K7/08 , H03L7/0891 , H03L7/0895 , H03L7/0898 , H03L7/091 , H03L7/093 , H03L7/18 , H03L7/1974
摘要： An example a phase-locked loop (PLL) circuit includes a sampling phase detector configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further includes a charge pump configured to generate a second control current based on the first control current and the pulse signal. The PLL further includes a loop filter configured to filter the second control current and generate an oscillator control voltage. The PLL further includes a voltage controlled oscillator (VCO) configured to generate an output clock based on the oscillator control voltage. The PLL further includes a frequency divider configured to generate the reference clock from the output clock.
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公开(公告)号：US09608644B1
公开(公告)日：2017-03-28
申请号：US15172442
申请日：2016-06-03
申请人： Xilinx, Inc.
发明人： Mayank Raj , Parag Upadhyaya , Adebabay M. Bekele
CPC分类号： H03L7/087 , H03L7/081 , H03L7/0895 , H03L7/091 , H03L7/095 , H03L7/1075 , H03L7/113
摘要： An example phase-locked loop (PLL) circuit includes a voltage controlled oscillator (VCO) configured to generate an output clock based on an oscillator control voltage, a sub-sampling phase detector configured to receive a reference clock and the output clock, and a phase frequency detector configured to receive the reference clock and a feedback clock. The PLL circuit includes a charge pump configured to generate a charge pump current, a multiplexer circuit configured to select either output of the sub-sampling phase detector or output of the phase frequency detector to control the charge pump, and a lock detector configured to receive the reference clock, the feedback clock, and the output of the phase frequency detector to control the multiplexer. The PLL circuit includes a loop filter configured to filter the charge pump current and generate the oscillator control voltage, and a frequency divider configured to generate the reference clock from the output clock.
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公开(公告)号：US11469877B1
公开(公告)日：2022-10-11
申请号：US17400762
申请日：2021-08-12
申请人： XILINX, INC.
发明人： Mayank Raj , Parag Upadhyaya
摘要： Some examples described herein provide an integrated circuit comprising an auxiliary clock and data recovery (CDR) circuitry. The CDR circuitry is configured to oversample an incoming data signal and generate a locked clock signal. The auxiliary CDR circuitry may comprise a phase-locked loop (PLL) configured to receive the incoming data signal and generate the locked clock signal. The PLL may comprise a phase detector (PD) configured to receive the incoming data signal and capture a number of samples of the incoming data signal in response to a number of adjacent clock signals and minimum data transition thresholds implemented by an intersymbol interference (ISI) filter, the minimum data transition thresholds identifying minimum data transitions in the incoming data signal.
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公开(公告)号：US11005572B1
公开(公告)日：2021-05-11
申请号：US17093399
申请日：2020-11-09
申请人： XILINX, INC.
发明人： Ping Chuan Chiang , Mayank Raj , Chuan Xie , Stanley Y. Chen , Sandeep Kumar , Sukruth Pattanagiri , Parag Upadhyaya , Yohan Frans
摘要： Examples described herein generally relate to a temperature-locked loop for optical elements. In an example, a device includes a controller and a digital-to-analog converter (DAC). The controller includes a DC-controllable transimpedance stage (DCTS), a slicer circuit, and a processor. The DCTS is configured to be coupled to a photodiode. An input node of the slicer circuit is coupled to an output node of the DCTS. The processor has an input node coupled to an output node of the slicer circuit. The DAC has an input node coupled to an output node of the processor and is configured to be coupled to a heater. The processor is configured to control (i) the DCTS to reduce a DC component of a signal on the output node of the DCTS and (ii) an output voltage on the output node of the DAC, both based on a signal output by the slicer circuit.
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公开(公告)号：US20200287551A1
公开(公告)日：2020-09-10
申请号：US16291286
申请日：2019-03-04
申请人： Xilinx, Inc.
摘要： A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO), a first loop circuit, and a second loop circuit. The first loop circuit includes a first loop filter configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The second loop circuit includes a compensation circuit configured to receive a reference signal and the first signal, and provide a second VCO frequency control signal to the VCO.
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公开(公告)号：US20180013435A1
公开(公告)日：2018-01-11
申请号：US15206634
申请日：2016-07-11
申请人： Xilinx, Inc.
发明人： Jinyung Namkoong , Mayank Raj , Parag Upadhyaya , Vamshi Manthena , Catherine Hearne , Marc Erett
CPC分类号： H03L7/0891 , H03L7/0805 , H03L7/0995 , H03L7/24 , H03M9/00
摘要： A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.
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