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公开(公告)号：US11636884B2
公开(公告)日：2023-04-25
申请号：US17587610
申请日：2022-01-28
Inventor： Yu-Der Chih
Abstract: A system includes: a processor; a register configured to store a plurality of words, non-volatile memory having a plurality of cells, each cell corresponding to one of the words of the register, and wherein the each cell of the plurality of cells are set to an initial reset value; a first controller that in response to a loss in power: determines the word stored by the register; and changes the initial reset value of the cell of the non-volatile memory corresponding to the determined word stored by the register to a set value; a second controller that in response to detecting a restoration in power: identifies the cell having the set value; writes the word corresponding to the identified cell to the register; and resets the cells of the non-volatile memory to the initial reset value.
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公开(公告)号：US11621037B2
公开(公告)日：2023-04-04
申请号：US17375608
申请日：2021-07-14
Inventor： Yuhsiang Chen , Shao-Yu Chou , Chun-Hao Chang , Min-Shin Wu , Yu-Der Chih
IPC: G11C11/41 , G11C11/419 , G11C11/418 , G11C11/409 , G11C11/413 , G11C7/10
Abstract: Memories are provided. A memory includes a first memory array, a second memory array and a read circuit. The first memory array is configured to store first data. The second memory array is configured to store second data that is complementary to the first data. The read circuit includes a decoding circuit, a sensing circuit and an output buffer. The decoding circuit is configured to provide a first signal according to the first data and a second signal according to the second data in response to an address signal. The sensing circuit is configured to provide a first sensing signal according to a reference signal and the first signal, and a second sensing signal according to the reference signal and the second signal. The output buffer is configured to provide the first sensing signal or the second sensing signal as an output according to a control signal.
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公开(公告)号：US11609815B1
公开(公告)日：2023-03-21
申请号：US17461532
申请日：2021-08-30
Inventor： Zheng-Jun Lin , Pei-Ling Tseng , Hsueh-Chih Yang , Chung-Cheng Chou , Yu-Der Chih
Abstract: A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.
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公开(公告)号：US20220415373A1
公开(公告)日：2022-12-29
申请号：US17884650
申请日：2022-08-10
Inventor： Yi-Chun Shih , Chia-Fu Lee , Yu-Der Chih , Jonathan Tsung-Yung Chang
Abstract: Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.
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公开(公告)号：US11495294B2
公开(公告)日：2022-11-08
申请号：US17106725
申请日：2020-11-30
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih , Pei-Ling Tseng
Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.
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Patent Agency Ranking
公开(公告)号：US11442482B2
公开(公告)日：2022-09-13
申请号：US17010064
申请日：2020-09-02
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih , Chin-I Su
Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.
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公开(公告)号：US20220253282A1
公开(公告)日：2022-08-11
申请号：US17532632
申请日：2021-11-22
Inventor： Chia-Fu Lee , Po-Hao Lee , Yi-Chun Shih , Yu-Der Chih
IPC: G06F7/501 , G06F7/506 , H03K19/0185 , H03K19/21
Abstract: In some aspects of the present disclosure, an adder tree circuit is disclosed. In some aspects, the adder tree circuit includes a plurality of full adders (FAs) including: a first subgroup of FAs, wherein each FA of the first subgroup includes a first number of transistors; and a second subgroup of FAs, wherein each FA of the second subgroup includes a second number of transistors, the first number being greater than the second number; wherein each FA of the first subgroup receives a first input from a first one of the second subgroup of FAs and a second input from a second one of the second subgroup of FAs, and each FA provides a first output to a third one of the second subgroup of FAs and a second output to a fourth one of the second subgroup of FAs.
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18.发明申请公开(公告)号：US20220236869A1
公开(公告)日：2022-07-28
申请号：US17155362
申请日：2021-01-22
Inventor： Yu-Der Chih , Chi-Fu Lee , Jonathan Tsung-Yung Chang
IPC: G06F3/06 , G11C11/419 , G06F7/544
Abstract: An in-memory computing device includes in some examples a two-dimensional array of memory cells arranged in rows and columns, each memory cell made of a nine-transistor current-based SRAM. Each memory cell includes a six-transistor SRAM cell and a current source coupled by a switching transistor, which is controlled by input signals on an input line, to an output line associates with the column of memory cells the memory cell is in. The current source includes a switching transistor controlled by the state of the six-transistor SRAM cell, and a current regulating transistor adapted to generate a current at a level determined by a control signal applied at the gate. The control signal can be set such that the total current in each output line is increased by a factor of 2 in each successive column of the memory cells.
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公开(公告)号：US11309022B2
公开(公告)日：2022-04-19
申请号：US17135169
申请日：2020-12-28
Inventor： Chien-An Lai , Chung-Cheng Chou , Yu-Der Chih
Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.
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公开(公告)号：US20220093142A1
公开(公告)日：2022-03-24
申请号：US17543046
申请日：2021-12-06
Inventor： Yi-Chun Shih , Chia-Fu Lee , Yu-Der Chih
Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.
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