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公开(公告)号：US20230386974A1
公开(公告)日：2023-11-30
申请号：US18361917
申请日：2023-07-31
发明人： Jen-Chun Liao , Sung-Yueh Wu , Chien-Ling Hwang , Ching-Hua Hsieh
IPC分类号： H01L23/48 , H01L23/15 , H01L21/768 , H01L23/498 , H01L21/56 , H01L23/538 , H01L23/31
CPC分类号： H01L23/481 , H01L23/15 , H01L21/76898 , H01L23/49838 , H01L21/56 , H01L23/5385 , H01L23/5386 , H01L23/3128 , H01L23/49833
摘要： A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.
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公开(公告)号：US20220293505A1
公开(公告)日：2022-09-15
申请号：US17199348
申请日：2021-03-11
发明人： Sung-Yueh Wu , Chien-Ling Hwang , Jen-Chun Liao , Ching-Hua Hsieh , Pei-Hsuan Lee , Chia-Hung Liu
IPC分类号： H01L23/498 , H01L23/31 , H01L21/48
摘要： A package structure includes a carrier substrate, a die, and a first redistribution structure. The carrier substrate has a first surface and a second surface opposite to the first surface. The carrier substrate includes an insulating body and through carrier vias (TCV) embedded in the insulating body. The die is disposed over the firs surface of the carrier substrate. The die is electrically connected to the TCVs. The first redistribution structure is disposed on the second surface of the carrier substrate.
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公开(公告)号：US12027494B2
公开(公告)日：2024-07-02
申请号：US17314017
申请日：2021-05-06
发明人： Hao-Yi Tsai , Tzuan-Horng Liu , Chien-Ling Hwang
IPC分类号： H01L21/768 , H01L21/48 , H01L21/56 , H01L21/66 , H01L21/68 , H01L23/00 , H01L23/31 , H01L23/495 , H01L23/498 , H01L23/522 , H01L23/528 , H01L23/532 , H01L23/538 , H01L25/065
CPC分类号： H01L25/0657 , H01L21/56 , H01L23/31 , H01L23/49816 , H01L23/5384 , H01L23/5385 , H01L24/14
摘要： A semiconductor device includes an integrated circuit, first conductive features, second conductive features, a package structure, and an encapsulant. The integrated circuit has an active surface and a rear surface opposite to the active surface. The first conductive features surround the integrated circuit. The second conductive features are stacked on the first conductive features. The package structure is disposed on the second conductive features and the rear surface of the integrated circuit. The encapsulant laterally encapsulates the integrated circuit, the first conductive features, the second conductive features, and the package structure.
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公开(公告)号：US11764127B2
公开(公告)日：2023-09-19
申请号：US17185966
申请日：2021-02-26
发明人： Jen-Chun Liao , Sung-Yueh Wu , Chien-Ling Hwang , Ching-Hua Hsieh
IPC分类号： H01L23/48 , H01L23/15 , H01L21/768 , H01L23/498 , H01L21/56 , H01L23/538 , H01L23/31
CPC分类号： H01L23/481 , H01L21/56 , H01L21/76898 , H01L23/15 , H01L23/3128 , H01L23/49833 , H01L23/49838 , H01L23/5385 , H01L23/5386
摘要： A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.
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公开(公告)号：US11756872B2
公开(公告)日：2023-09-12
申请号：US17199348
申请日：2021-03-11
发明人： Sung-Yueh Wu , Chien-Ling Hwang , Jen-Chun Liao , Ching-Hua Hsieh , Pei-Hsuan Lee , Chia-Hung Liu
IPC分类号： H01L23/495 , H01L23/498 , H01L23/31 , H01L21/48 , H01L23/00
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/4857 , H01L23/3128 , H01L23/49822 , H01L23/49833 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/73253
摘要： A package structure includes a carrier substrate, a die, and a first redistribution structure. The carrier substrate has a first surface and a second surface opposite to the first surface. The carrier substrate includes an insulating body and through carrier vias (TCV) embedded in the insulating body. The die is disposed over the firs surface of the carrier substrate. The die is electrically connected to the TCVs. The first redistribution structure is disposed on the second surface of the carrier substrate.
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公开(公告)号：US20230268316A1
公开(公告)日：2023-08-24
申请号：US17674847
申请日：2022-02-18
发明人： Sung-Yueh Wu , Chien-Ling Hwang , Jen-Chun Liao , Ching-Hua Hsieh
IPC分类号： H01L23/00 , H01L23/498 , H01L23/31 , H01L21/56
CPC分类号： H01L24/96 , H01L24/16 , H01L23/49822 , H01L23/3114 , H01L21/561 , H01L24/81 , H01L2224/16225 , H01L2224/81947
摘要： A package structure includes a semiconductor device including a conductive feature, a joint layer, a pillar structure, an encapsulant and a RDL structure. The joint layer is disposed on the conductive feature. The pillar structure is disposed on and coupled to the semiconductor device through the joint layer. The encapsulant laterally encapsulates the semiconductor device and the pillar structure. The RDL structure is electrically connected to the semiconductor device.
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公开(公告)号：US20220367310A1
公开(公告)日：2022-11-17
申请号：US17320198
申请日：2021-05-13
发明人： Pei-Hsuan Lee , Ching-Hua Hsieh , Chien-Ling Hwang
摘要： A package system and a manufacturing method thereof are provided. The package system includes a semiconductor package and a thermal-dissipating structure. The semiconductor package includes a first surface and a second surface opposing to each other, and a planarity of the second surface is greater than that of the first surface. The thermal-dissipating structure includes a first plate secured to the semiconductor package, a gasket interposed between the first plate and the semiconductor package, a second plate secured to the semiconductor package opposite to the first plate, and a first thermal interface material layer interposed between the second plate and the second surface of the semiconductor package. The gasket includes a plurality of hollow regions corresponding to portions of the first surface of the semiconductor package.
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公开(公告)号：US20240312859A1
公开(公告)日：2024-09-19
申请号：US18674903
申请日：2024-05-26
发明人： Pei-Hsuan Lee , Ching-Hua Hsieh , Chien-Ling Hwang
摘要： A manufacturing method of a package system includes: providing a base plate with a first thermal interface material (TIM) layer; placing a semiconductor package on the first TIM layer over the base plate, wherein the semiconductor package comprises a plurality of packaging units arranged in an array and a plurality of electrical connectors surrounding the array of the plurality of packaging units; stacking a gasket and a top plate on the array of the plurality of packaging units, wherein the gasket is interposed between the top plate and the array of the plurality of packaging units; and securing the top plate, the gasket, the plurality of packaging units, and the base plate together through a plurality of fasteners, wherein each of the plurality of fasteners is arranged at a gap between two of the adjacent packaging units.
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公开(公告)号：US12062832B2
公开(公告)日：2024-08-13
申请号：US17383403
申请日：2021-07-22
CPC分类号： H01Q1/2283 , H01L21/4846 , H01L23/66 , H01L24/13 , H01L24/24 , H01L24/32 , H01L24/73 , H01Q1/40 , H01L2223/6677 , H01L2224/13024 , H01L2224/24101 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267
摘要： A method of manufacturing an electronic device includes providing a core dielectric layer with two conductive layers formed on two opposite surfaces of the core dielectric layer, and removing at least a portion of each of the two conductive layers to respectively form an antenna pattern and a circuit pattern of a chip package at the two opposite surfaces of the core dielectric layer.
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公开(公告)号：US12040255B2
公开(公告)日：2024-07-16
申请号：US18361917
申请日：2023-07-31
发明人： Jen-Chun Liao , Sung-Yueh Wu , Chien-Ling Hwang , Ching-Hua Hsieh
IPC分类号： H01L23/48 , H01L21/56 , H01L21/768 , H01L23/15 , H01L23/31 , H01L23/498 , H01L23/538
CPC分类号： H01L23/481 , H01L21/56 , H01L21/76898 , H01L23/15 , H01L23/3128 , H01L23/49833 , H01L23/49838 , H01L23/5385 , H01L23/5386
摘要： A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.
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