公开(公告)号：US09520446B2

公开(公告)日：2016-12-13

申请号：US14450809

申请日：2014-08-04

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Yu-Wei Ting ,  Chi-Wen Liu ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: H01L29/66 ,  H01L27/24 ,  H01L27/22

CPC classification number: H01L27/2454 ,  H01L27/228 ,  H01L27/2463 ,  H01L29/4236 ,  H01L29/7827

Abstract: Some embodiments of the present disclosure relate to a memory array comprising memory cells having vertical gate-all-around (GAA) selection transistors. In some embodiments, the memory array has a source region disposed within an upper surface of a semiconductor body, and a semiconductor pillar of semiconductor material extending outward from the upper surface of the semiconductor body and having a channel region and an overlying drain region. A gate region vertically overlies the source region at a position laterally separated from sidewalls of the channel region by a gate dielectric layer. A first metal contact couples the drain region to a data storage element that stores data. The vertical GAA selection transistors provide for good performance, while decreasing the size of the selection transistor relative to a planar MOSFET, so that the selection transistors do not negatively impact the size of the memory array.

Abstract translation: 本公开的一些实施例涉及包括具有垂直栅极全周（GAA）选择晶体管的存储器单元的存储器阵列。 在一些实施例中，存储器阵列具有设置在半导体本体的上表面内的源极区域和从半导体本体的上表面向外延伸并具有沟道区域和上覆漏极区域的半导体材料的半导体柱。 栅极区域通过栅极介电层在与沟道区域的侧壁横向分离的位置处垂直地覆盖源极区域。 第一金属触点将漏极区域耦合到存储数据的数据存储元件。 垂直GAA选择晶体管提供良好的性能，同时相对于平面MOSFET减小选择晶体管的尺寸，使得选择晶体管不会对存储器阵列的尺寸产生负面影响。

公开(公告)号：US20160099291A1

公开(公告)日：2016-04-07

申请号：US14967697

申请日：2015-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yang Tsai ,  Yu-Wei Ting ,  Kuo-Ching Huang

IPC: H01L27/24 ,  H01L23/528 ,  H01L45/00

CPC classification number: H01L27/2463 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.

Abstract translation: 一些实施例涉及包括设置在半导体衬底上的存储器单元阵列的集成电路器件。 第一金属线阵列被布置在衬底上的第一高度处并连接到阵列的存储器单元。 每个第一金属线具有第一横截面积。 第二金属线阵列设置在衬底上的第二高度处，并连接到阵列的存储单元。 每个第二金属线具有大于第一横截面积的第二横截面积。

公开(公告)号：US20140177330A1

公开(公告)日：2014-06-26

申请号：US13723762

申请日：2012-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Wei Ting ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: H01L29/732 ,  H01L29/82 ,  H01L45/00 ,  G11C11/40

CPC classification number: H01L29/732 ,  G11C11/161 ,  G11C11/40 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/79 ,  H01L27/226 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2445 ,  H01L27/2454 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/82 ,  H01L45/04

Abstract: Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.

Abstract translation: 本公开的一些方面涉及存储器设备。 存储器件包括具有第一导电类型并且耦合到存储器件的源极线的集电极区域。 基极区域形成在集电极区域上并且具有第二导电类型。 栅极结构耦合到基极区域并用作存储器件的第一和第二相邻存储器单元的共享字线。 第一和第二发射极区域形成在基极区域上并且具有第一导电类型。 第一和第二发射极区域布置在栅极结构的相对侧上。 第一和第二触点分别从第一和第二发射极区域向上延伸，并分别将第一和第二发射极区域分别耦合到第一和第二相邻存储器单元的第一和第二数据存储元件。

公开(公告)号：US20170092748A1

公开(公告)日：2017-03-30

申请号：US15371801

申请日：2016-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Ting ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: H01L29/732 ,  G11C13/00 ,  H01L27/24 ,  G11C11/16 ,  H01L29/66 ,  H01L27/22

CPC classification number: H01L29/732 ,  G11C11/161 ,  G11C11/40 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/79 ,  H01L27/226 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2445 ,  H01L27/2454 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/82 ,  H01L45/04

Abstract: Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.

公开(公告)号：US09230647B2

公开(公告)日：2016-01-05

申请号：US14152244

申请日：2014-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yang Tsai ,  Yu-Wei Ting ,  Kuo-Ching Huang

IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L27/2463 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes an array of RRAM cells, an array of bit lines for the array of RRAM cells, and an array of source lines for the array of RRAM cells. Both the source lines and the bit lines are in metal interconnect layers above the RRAM cells. The source line are thereby provided with a higher than conventional wire size, which increases the reset speed by approximately one order of magnitude. The lifetime of the RRAM transistors and the durability of the RRAM device are consequentially improved to a similar degree.

Abstract translation: 集成电路设备包括RRAM单元阵列，RRAM单元阵列的位线阵列，以及RRAM单元阵列的源极阵列。 源极线和位线都位于RRAM单元上方的金属互连层中。 因此，源极线被提供有高于常规电线尺寸，其将复位速度提高约一个数量级。 RRAM晶体管的寿命和RRAM器件的耐用性因此相应地得到改善。

公开(公告)号：US20150349086A1

公开(公告)日：2015-12-03

申请号：US14826318

申请日：2015-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Ting ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: H01L29/66 ,  H01L27/24 ,  H01L27/22

CPC classification number: H01L29/732 ,  G11C11/161 ,  G11C11/40 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/79 ,  H01L27/226 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2445 ,  H01L27/2454 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/82 ,  H01L45/04

Abstract: Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.

Abstract translation: 本公开的一些方面涉及存储器设备。 存储器件包括具有第一导电类型并且耦合到存储器件的源极线的集电极区域。 基极区域形成在集电极区域上并且具有第二导电类型。 栅极结构耦合到基极区域并用作存储器件的第一和第二相邻存储器单元的共享字线。 第一和第二发射极区域形成在基极区域上并且具有第一导电类型。 第一和第二发射极区域布置在栅极结构的相对侧上。 第一和第二触点分别从第一和第二发射极区域向上延伸，并分别将第一和第二发射极区域分别耦合到第一和第二相邻存储器单元的第一和第二数据存储元件。

公开(公告)号：US09178040B2

公开(公告)日：2015-11-03

申请号：US13674204

申请日：2012-11-12

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Yu-Wei Ting ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/22 ,  H01L27/24

CPC classification number: H01L29/66666 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463

Abstract: Some embodiments of the present disclosure relate to a vertical MOSFET selection transistor that is configured to suppress leakage voltage in the memory cell without limiting the size of the memory cell. The memory selection transistor has a semiconductor body with first and second trenches that define a raised semiconductor structure having a source region, a channel region, and a drain region. A gate structure has a first gate electrode in the first trench, which extends vertically along a first side of the raised semiconductor structure, and a second gate electrode in the second trench, which extends vertically along an opposite, second side of the raised semiconductor structure. The first and second gate electrodes collectively control the flow of current between the source and drain region in the raised semiconductor structure. An electrical contact couples the drain region to a data storage element configured to store data.

Abstract translation: 本公开的一些实施例涉及垂直MOSFET选择晶体管，其被配置为在不限制存储器单元的尺寸的情况下抑制存储单元中的泄漏电压。 存储器选择晶体管具有半导体本体，其具有限定具有源极区，沟道区和漏极区的凸起半导体结构的第一和第二沟槽。 栅极结构在第一沟槽中具有第一栅电极，其沿凸起半导体结构的第一侧垂直延伸，第二沟槽中的第二栅电极沿凸起半导体结构的相对的第二侧垂直延伸 。 第一和第二栅电极共同控制凸起半导体结构中的源极和漏极区域之间的电流流动。 电触点将漏极区域耦合到被配置为存储数据的数据存储元件。

公开(公告)号：US20140339631A1

公开(公告)日：2014-11-20

申请号：US14450809

申请日：2014-08-04

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Yu-Wei Ting ,  Chi-Wen Liu ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: H01L29/78 ,  H01L27/24 ,  H01L27/22 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L27/2454 ,  H01L27/228 ,  H01L27/2463 ,  H01L29/4236 ,  H01L29/7827

Abstract: Some embodiments of the present disclosure relate to a memory array comprising memory cells having vertical gate-all-around (GAA) selection transistors. In some embodiments, the memory array has a source region disposed within an upper surface of a semiconductor body, and a semiconductor pillar of semiconductor material extending outward from the upper surface of the semiconductor body and having a channel region and an overlying drain region. A gate region vertically overlies the source region at a position laterally separated from sidewalls of the channel region by a gate dielectric layer. A first metal contact couples the drain region to a data storage element that stores data. The vertical GAA selection transistors provide for good performance, while decreasing the size of the selection transistor relative to a planar MOSFET, so that the selection transistors do not negatively impact the size of the memory array.

Abstract translation: 本公开的一些实施例涉及包括具有垂直栅极全周（GAA）选择晶体管的存储器单元的存储器阵列。 在一些实施例中，存储器阵列具有设置在半导体本体的上表面内的源极区域和从半导体本体的上表面向外延伸并具有沟道区域和上覆漏极区域的半导体材料的半导体柱。 栅极区域通过栅极介电层在与沟道区域的侧壁横向分离的位置处垂直地覆盖源极区域。 第一金属触点将漏极区域耦合到存储数据的数据存储元件。 垂直GAA选择晶体管提供良好的性能，同时相对于平面MOSFET减小选择晶体管的尺寸，使得选择晶体管不会对存储器阵列的尺寸产生负面影响。

公开(公告)号：US20140131794A1

公开(公告)日：2014-05-15

申请号：US13674204

申请日：2012-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Yu-Wei Ting ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66666 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463

Abstract: Some embodiments of the present disclosure relate to a vertical MOSFET selection transistor that is configured to suppress leakage voltage in the memory cell without limiting the size of the memory cell. The memory selection transistor has a semiconductor body with first and second trenches that define a raised semiconductor structure having a source region, a channel region, and a drain region. A gate structure has a first gate electrode in the first trench, which extends vertically along a first side of the raised semiconductor structure, and a second gate electrode in the second trench, which extends vertically along an opposite, second side of the raised semiconductor structure. The first and second gate electrodes collectively control the flow of current between the source and drain region in the raised semiconductor structure. An electrical contact couples the drain region to a data storage element configured to store data.

Abstract translation: 本公开的一些实施例涉及垂直MOSFET选择晶体管，其被配置为在不限制存储器单元的尺寸的情况下抑制存储单元中的泄漏电压。 存储器选择晶体管具有半导体本体，其具有限定具有源极区，沟道区和漏极区的凸起半导体结构的第一和第二沟槽。 栅极结构在第一沟槽中具有第一栅电极，其沿凸起半导体结构的第一侧垂直延伸，第二沟槽中的第二栅电极沿凸起半导体结构的相对的第二侧垂直延伸 。 第一和第二栅电极共同控制凸起半导体结构中的源极和漏极区域之间的电流流动。 电触点将漏极区域耦合到被配置为存储数据的数据存储元件。