知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

42 records (took 0.019 seconds)

    ELECTROMAGNETIC SHIELDING METAL-INSULATOR-METAL CAPACITOR STRUCTURE
    12.
    发明申请
    ELECTROMAGNETIC SHIELDING METAL-INSULATOR-METAL CAPACITOR STRUCTURE 审中-公开

    公开(公告)号：US20200020644A1

    公开(公告)日：2020-01-16

    申请号：US16043355

    申请日：2018-07-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hui Yu LEE ,  Chin-Chou Liu ,  Cheng-Hung Yeh ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Ka Fai Chang

    IPC: H01L23/552 ,  H01L49/02 ,  H01L23/498 ,  G06F17/50 ,  H01L23/522

    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.

    Standard Cells and Variations Thereof Within a Standard Cell Library
    14.
    发明申请
    Standard Cells and Variations Thereof Within a Standard Cell Library 审中-公开

    公开(公告)号：US20190064770A1

    公开(公告)日：2019-02-28

    申请号：US15800693

    申请日：2017-11-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Hsiung CHEN ,  Jerry Chang-Jui Kao ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Shao-Huan Wang ,  XinYong Wang ,  Yi-Kan Cheng ,  Chun-Chen Chen

    IPC: G05B19/4097 ,  G06F17/50 ,  H01L27/02

    Abstract: Exemplary embodiments for multiple standard cell libraries are disclosed that include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations have similar functionality as their one or more standard cells but are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for analog circuitry and/or digital circuitry of an electronic device. In an exemplary embodiment, a semiconductor foundry and/or semiconductor technology node can impose one or more electronic design constraints on the placement of the one or more standard cells onto an electronic device design real estate. In some situations, some of the one or more standard cells are unable to satisfy the one or more electronic design constraints when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

    Static timing analysis method and system considering capacitive coupling and double patterning mask misalignment
    15.
    发明授权
    Static timing analysis method and system considering capacitive coupling and double patterning mask misalignment 有权
    静态时序分析方法和系统考虑电容耦合和双重图案掩模失准

    公开(公告)号：US08612912B1

    公开(公告)日：2013-12-17

    申请号：US13723248

    申请日：2012-12-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Hao Chen ,  Yi-Kan Cheng

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/504 ,  G06F2217/84

    Abstract: A method for analyzing an IC design, comprises: using a computer implemented electronic design automation tool to perform a parasitic RC extraction for a layout of the IC design, the parasitic RC extraction outputting for each of a plurality of routing paths, a nominal capacitive coupling, a minimum capacitive coupling and a maximum capacitive coupling, where the minimum and maximum capacitive couplings correspond to circuit patterning in the presence of double patterning mask misalignments; and performing one of a setup time analysis or a hold time analysis of the IC design using a computer implemented static timing analysis tool. For a given flip-flop having a launch path and a capture path, the setup or hold time analysis is performed using the minimum capacitive coupling for one of the launch and capture paths and the maximum capacitive coupling for the other of the launch and capture paths.

    Abstract translation: 一种用于分析IC设计的方法，包括：使用计算机实现的电子设计自动化工具来执行用于IC设计布局的寄生RC提取，针对多个路由路径中的每一个的寄生RC提取输出，标称电容耦合 最小电容耦合和最大电容耦合，其中最小和最大电容耦合在存在双重图案化掩模未对准的情况下对应于电路图案化; 并使用计算机实现的静态时序分析工具执行IC设计的建立时间分析或保持时间分析之一。 对于具有发射路径和捕获路径的给定触发器，使用用于发射和捕获路径中的一个的最小电容耦合和用于另一个发射和捕获路径的最大电容耦合来执行建立或保持时间分析 。

    SOIC CHIP ARCHITECTURE
    17.
    发明申请
    SOIC CHIP ARCHITECTURE 有权

    公开(公告)号：US20220375827A1

    公开(公告)日：2022-11-24

    申请号：US17875199

    申请日：2022-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Fong-Yuan Chang ,  Chin-Chou Liu ,  Chin-Her Chien ,  Cheny-hung Yeh ,  Hui Yu Lee ,  Po-Hsiang Huang ,  Yi-Kan Cheng

    IPC: H01L23/48 ,  H01L23/00 ,  H01L27/06

    Abstract: A device, such as a computer system, includes an interconnection device die and at least two additional device dice. The additional device dies can be system on integrated chip (SOIC) dies laying face to face (F2F) on the interconnection device die. The interconnection device die includes electrical connectors on one surface, enabling connection to and/or among the additional device dice. The interconnection device die includes at least one redistribution circuit structure, which may be an integrated fan out (InFO) structure, and at least one through-silicon via (TSV). The TSV enables connection between a signal line, power line or ground line, from an opposite surface of the interconnection device die to the redistribution circuit structure and/or electrical connectors. At least one of the additional dice can be a three-dimensional integrated circuit (3DIC) die with face to back (F2B) stacking.

    Static timing analysis method and system considering capacitive coupling and double patterning mask misalignment
    19.
    发明授权
    Static timing analysis method and system considering capacitive coupling and double patterning mask misalignment 有权
    静态时序分析方法和系统考虑电容耦合和双重图案掩模失准

    公开(公告)号：US08972919B2

    公开(公告)日：2015-03-03

    申请号：US14076330

    申请日：2013-11-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Hao Chen ,  Yi-Kan Cheng

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/504 ,  G06F2217/84

    Abstract: A method for analyzing an IC design, comprises: using a computer implemented electronic design automation tool to perform a parasitic RC extraction for a layout of the IC design, the parasitic RC extraction outputting for each of a plurality of routing paths, a nominal capacitive coupling, a minimum capacitive coupling and a maximum capacitive coupling, where the minimum and maximum capacitive couplings correspond to circuit patterning in the presence of double patterning mask misalignments; and performing one of a setup time analysis or a hold time analysis of the IC design using a computer implemented static timing analysis tool. For a given flip-flop having a launch path and a capture path, the setup or hold time analyses is performed using the minimum capacitive coupling for one of the launch and capture paths and the maximum capacitive coupling for the other of the launch and capture paths.

    Abstract translation: 一种用于分析IC设计的方法，包括：使用计算机实现的电子设计自动化工具来执行用于IC设计布局的寄生RC提取，针对多个路由路径中的每一个的寄生RC提取输出，标称电容耦合 最小电容耦合和最大电容耦合，其中最小和最大电容耦合在存在双重图案化掩模未对准的情况下对应于电路图案化; 并使用计算机实现的静态时序分析工具执行IC设计的建立时间分析或保持时间分析之一。 对于具有发射路径和捕获路径的给定触发器，使用用于发射和捕获路径中的一个的最小电容耦合和用于另一个发射和捕获路径的最大电容耦合来执行建立或保持时间分析 。

    Parasitic component library and method for efficient circuit design and simulation using the same
    20.
    发明授权
    Parasitic component library and method for efficient circuit design and simulation using the same 有权
    寄生元件库和方法用于高效电路设计和仿真使用

    公开(公告)号：US08893066B2

    公开(公告)日：2014-11-18

    申请号：US13728295

    申请日：2012-12-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Sheng Chen ,  Tsun-Yu Yang ,  Wei-Yi Hu ,  Tao Wen Chung ,  Jui-Feng Kuan ,  Yi-Kan Cheng

    IPC: G06F9/455 ,  G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5045

    Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.

    Abstract translation: 一种用于电路设计的方法包括嵌入一个或多个参数化单元的寄生感知库。 寄生感知库用于将表示电路的一些但不是全部寄生效应的网络插入到电路原理图中，使单个电路原理图用于电路仿真，电路的寄生校验和LVS（布局与原理图）检查 。 电路设计过程只需要单一电路原理图，并形成掩模组。 识别单个电路原理图的关键路径，并提取寄生效应并将其插入原理图，使得能够执行寄生验证的预估计，并使用具有一些寄生效应的电路原理图进行LVS检查， 其中包括布局的所有寄生分量的后布局模拟。

Patent Agency Ranking