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公开(公告)号：US20210142832A1
公开(公告)日：2021-05-13
申请号：US17156383
申请日：2021-01-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ku-Feng LIN , Yu-Der Chih , Yi-Chun Shih , Chia-Fu Lee
Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.
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公开(公告)号：US10861572B2
公开(公告)日：2020-12-08
申请号：US16856553
申请日：2020-04-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Der Chih , Chien-Yin Liu , Yi-Chun Shih
Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.
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公开(公告)号：US12080375B2
公开(公告)日：2024-09-03
申请号：US18232768
申请日：2023-08-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ku-Feng Lin , Yu-Der Chih , Yi-Chun Shih , Chia-Fu Lee
CPC classification number: G11C7/065 , G11C7/08 , G11C11/14 , G11C13/004 , H01L27/10
Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.
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公开(公告)号：US11783873B2
公开(公告)日：2023-10-10
申请号：US17737734
申请日：2022-05-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ku-Feng Lin , Yu-Der Chih , Yi-Chun Shih , Chia-Fu Lee
CPC classification number: G11C7/065 , G11C7/08 , G11C11/14 , G11C13/004 , H01L27/10
Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.
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公开(公告)号：US11211106B2
公开(公告)日：2021-12-28
申请号：US16715682
申请日：2019-12-16
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chia-Fu Lee , Yu-Der Chih , Hon-Jarn Lin , Yi-Chun Shih
Abstract: A device includes a first reference storage unit, a second reference storage unit, a first reference switch, and a second reference switch. The first reference switch includes a first terminal coupled to a first reference bit line, a second terminal coupled to the first reference storage unit, and a control terminal coupled a reference word line. The second reference switch includes a first terminal coupled to a second reference bit line, a second terminal coupled to the second reference storage unit, and a control terminal coupled the reference word line. The first reference storage unit is configured to receive a bit data through the first reference switch, and to generate a first signal having a first logic state.
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Patent Agency Ranking
公开(公告)号：US10157654B2
公开(公告)日：2018-12-18
申请号：US15667600
申请日：2017-08-02
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chia-Fu Lee , Yu-Der Chih , Hon-Jarn Lin , Yi-Chun Shih
Abstract: A device includes memory cells, a reference circuit, and a sensing unit. The reference circuit includes a first reference switch, a second reference switch, and reference storage units. The first reference switch is turned on when a reference word line is activated. The second reference switch is turned on when the reference word line is activated. The reference storage units include a first reference storage unit and a second reference storage unit. The first reference storage unit generates a first signal having a first logic state when the first reference switch is turned on. The second reference storage unit generates a second signal having a second logic state when the second reference switch is turned on. The sensing unit determines a logic state of the bit data of one of the memory cells according to the first signal and the second signal.
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公开(公告)号：US09728231B1
公开(公告)日：2017-08-08
申请号：US15145658
申请日：2016-05-03
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Po-Hao Lee , Yi-Chun Shih
CPC classification number: G11C5/147 , G11C7/14 , G11C13/0038 , G11C16/30 , G11C29/56 , G11C2029/5002
Abstract: A device includes a voltage regulator, an auxiliary signal generator, and a circuit cell. The voltage regulator is configured to output a write voltage. The auxiliary signal generator is configured to output an auxiliary signal. The circuit cell is configured to receive both of the write voltage and the auxiliary signal according to a first select signal and a second select signal.
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公开(公告)号：US12164317B2
公开(公告)日：2024-12-10
申请号：US18232772
申请日：2023-08-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-An Chang , Chia-Fu Lee , Yu-Der Chih , Yi-Chun Shih
IPC: G05F1/56
Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.
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公开(公告)号：US11797831B2
公开(公告)日：2023-10-24
申请号：US17883594
申请日：2022-08-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Win-San Khwa , Yu-Der Chih , Yi-Chun Shih , Chien-Yin Liu
CPC classification number: G06N3/063 , G06N3/08 , G11C11/54 , G11C29/04 , G11C7/1006
Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.
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公开(公告)号：US11373690B2
公开(公告)日：2022-06-28
申请号：US17156383
申请日：2021-01-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ku-Feng Lin , Yu-Der Chih , Yi-Chun Shih , Chia-Fu Lee
Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.
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