公开(公告)号：US20170194335A1

公开(公告)日：2017-07-06

申请号：US14984034

申请日：2015-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Tzu-Yu Chen

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/51

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a logic region having a logic device disposed over a substrate and including a first metal gate electrode disposed over a first high-k gate dielectric layer and an embedded memory region disposed adjacent to the logic region. The embedded memory region has a non-volatile memory (NVM) device including a second metal gate electrode disposed over the high-k gate dielectric layer. By having HKMG structures in both the logic region and the memory region, IC performance is improved and further scaling becomes possible in emerging technology nodes.

公开(公告)号：US20240373645A1

公开(公告)日：2024-11-07

申请号：US18777063

申请日：2024-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Fu-Chen Chang ,  Chih-Hsiang Chang ,  Sheng-Hung Shih

IPC: H10B53/30 ,  G11C11/22 ,  H10B53/10

Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.

公开(公告)号：US20200075075A1

公开(公告)日：2020-03-05

申请号：US16267668

申请日：2019-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yong-Shiuan Tsair

IPC: G11C11/22 ,  H01L27/11592 ,  H01L27/1159 ,  H01L29/51

Abstract: In some embodiments, the present disclosure relates to a memory structure. The memory structure has a source region and a drain region disposed within a substrate. A select gate disposed over the substrate between the source region and the drain region. A ferroelectric random access memory (FeRAM) device is disposed over the substrate between the select gate and the source region. The FeRAM device includes a ferroelectric material arranged between the substrate and a conductive electrode.

公开(公告)号：US09793286B2

公开(公告)日：2017-10-17

申请号：US14984034

申请日：2015-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Tzu-Yu Chen

IPC: H01L29/792 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/51

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a logic region having a logic device disposed over a substrate and including a first metal gate electrode disposed over a first high-k gate dielectric layer and an embedded memory region disposed adjacent to the logic region. The embedded memory region has a non-volatile memory (NVM) device including a second metal gate electrode disposed over the high-k gate dielectric layer. By having HKMG structures in both the logic region and the memory region, IC performance is improved and further scaling becomes possible in emerging technology nodes.

公开(公告)号：US12114509B2

公开(公告)日：2024-10-08

申请号：US17712495

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Fu-Chen Chang ,  Chih-Hsiang Chang ,  Sheng-Hung Shih

IPC: H01L21/00 ,  G11C11/22 ,  H01L49/02 ,  H10B53/10 ,  H10B53/30

CPC classification number: H10B53/30 ,  G11C11/221 ,  H01L28/56 ,  H01L28/75 ,  H10B53/10

Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.

公开(公告)号：US11088203B2

公开(公告)日：2021-08-10

申请号：US16575663

申请日：2019-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Hsien Hsieh ,  Tzu-Yu Chen ,  Kuo-Chi Tu ,  Yuan-Tai Tseng

IPC: H01L27/00 ,  H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell.

公开(公告)号：US11037941B2

公开(公告)日：2021-06-15

申请号：US16558750

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yong-Shiuan Tsair

IPC: H01L27/11507 ,  H01L27/11509 ,  H01L21/311 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L21/266 ,  H01L21/321 ,  H01L29/51 ,  H01L21/3105 ,  H01L29/08 ,  H01L21/265

Abstract: A method for forming an integrated circuit (IC) and an IC are disclosed. The method for forming the IC includes: forming an isolation structure separating a memory semiconductor region from a logic semiconductor region; forming a memory cell structure on the memory semiconductor region; forming a memory capping layer covering the memory cell structure and the logic semiconductor region; performing a first etch into the memory capping layer to remove the memory capping layer from the logic semiconductor region, and to define a slanted, logic-facing sidewall on the isolation structure; forming a logic device structure on the logic semiconductor region; and performing a second etch into the memory capping layer to remove the memory capping layer from the memory semiconductor, while leaving a dummy segment of the memory capping layer that defines the logic-facing sidewall.

公开(公告)号：US20200343265A1

公开(公告)日：2020-10-29

申请号：US16394207

申请日：2019-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Chang ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Tzu-Yu Chen ,  Fu-Chen Chang

IPC: H01L27/11585 ,  G11C11/22 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: In some embodiments, the present disclosure relates to an integrated chip including one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric layers over a substrate. A bottom electrode is disposed over the one or more interconnect layers, and a top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts a first surface of the bottom electrode and a second surface of the top electrode. The ferroelectric layer includes a protrusion that extends past outer surfaces of the top electrode and the bottom electrode along a first direction that is perpendicular to a second direction that is normal to the first surface. The protrusion is confined between lines that extend along the first and second surface.

公开(公告)号：US11849588B2

公开(公告)日：2023-12-19

申请号：US17712543

申请日：2022-04-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu-Chen Chang ,  Kuo-Chi Tu ,  Tzu-Yu Chen ,  Sheng-Hung Shih

IPC: G11C11/22 ,  H10B51/30 ,  H01L49/02 ,  H10B51/10 ,  H10B53/00 ,  H10B53/30

CPC classification number: H10B51/30 ,  G11C11/223 ,  H01L28/57 ,  H01L28/60 ,  H10B51/10 ,  H10B53/00 ,  H10B53/30

Abstract: A method of forming a semiconductor device includes forming an inter-metal dielectric layer over a substrate; forming a first conductive line embedded in the inter-metal dielectric layer; forming a dielectric structure over the inter-metal dielectric layer and the first conductive line; etching the dielectric structure until the first conductive line is exposed; forming a bottom electrode layer on the exposed first conductive line such that the bottom electrode layer has an U-shaped when viewed in a cross section; forming a ferroelectric layer over the bottom electrode layer; forming a top electrode layer over the ferroelectric layer.

公开(公告)号：US11723213B2

公开(公告)日：2023-08-08

申请号：US17376531

申请日：2021-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Fu-Chen Chang

IPC: H10B53/30 ,  H01L49/02

CPC classification number: H10B53/30 ,  H01L28/60

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.