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公开(公告)号：US11017852B2
公开(公告)日：2021-05-25
申请号：US16700936
申请日：2019-12-02
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Kuo-Chi Tu , Chu-Jie Huang , Sheng-Hung Shih , Nai-Chao Su , Wen-Ting Chu
Abstract: A method of forming a memory device includes: forming a polish stop layer over a metallization layer in an inter-metal dielectric layer; performing an etching process to form an opening in the polish stop layer, in which a sidewall of the opening extends at an acute angle relative to a top surface of the polish stop layer; forming an electrode material in the opening and over the polish stop layer; planarizing the electrode material until a top surface of the polish stop layer is exposed so as to form a bottom electrode surrounded by the polish stop layer; and forming a stack of a resistance switching layer and a top electrode over the bottom electrode.
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公开(公告)号：US11011224B2
公开(公告)日：2021-05-18
申请号：US16700918
申请日：2019-12-02
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Kuo-Chi Tu , Chu-Jie Huang , Sheng-Hung Shih , Nai-Chao Su , Wen-Ting Chu
Abstract: A memory device includes a metal structure, a first dielectric layer, a bottom electrode, a second dielectric layer, a resistance switching layer, and a top electrode. The first dielectric layer surrounds the metal structure. The bottom electrode is in contact with a top surface of the metal structure. The second dielectric layer surrounds the bottom electrode, in which a top surface of the bottom electrode is higher than a top surface of the second dielectric layer. The resistance switching layer is over the bottom electrode. The top electrode is over the resistance switching layer.
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公开(公告)号：US10862029B2
公开(公告)日：2020-12-08
申请号：US16693566
申请日：2019-11-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsia-Wei Chen , Wen-Ting Chu , Kuo-Chi Tu , Chih-Yang Chang , Chin-Chieh Yang , Yu-Wen Liao , Wen-Chun You , Sheng-Hung Shih
Abstract: Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.
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公开(公告)号：US10763426B2
公开(公告)日：2020-09-01
申请号：US16552169
申请日：2019-08-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsia-Wei Chen , Chih-Yang Chang , Chin-Chieh Yang , Jen-Sheng Yang , Sheng-Hung Shih , Tung-Sheng Hsiao , Wen-Ting Chu , Yu-Wen Liao , I-Ching Chen
IPC: H01L43/02 , H01L23/538 , H01L43/12 , H01L27/22 , H01L45/00 , H01L21/768 , H01L27/24 , H01L43/08
Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
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公开(公告)号：US10700275B2
公开(公告)日：2020-06-30
申请号：US16227096
申请日：2018-12-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You
Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode via and a bottom electrode over a top of the bottom electrode via. A data storage layer is over the bottom electrode and a top electrode is over the data storage layer. A top electrode via is on an upper surface of the top electrode and is centered along a first line that is laterally offset from a second line centered upon a bottommost surface of the bottom electrode via. The first line is perpendicular to the upper surface of the top electrode and parallel to the second line.
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Patent Agency Ranking
公开(公告)号：US20190272873A1
公开(公告)日：2019-09-05
申请号：US16413937
申请日：2019-05-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.
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公开(公告)号：US20190229265A1
公开(公告)日：2019-07-25
申请号：US16372642
申请日：2019-04-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsia-Wei Chen , Wen-Ting Chu , Kuo-Chi Tu , Chih-Yang Chang , Chin-Chieh Yang , Yu-Wen Liao , Wen-Chun You , Sheng-Hung Shih
CPC classification number: H01L45/1233 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/122 , H01L45/124 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1666 , H01L45/1683
Abstract: Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.
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公开(公告)号：US10164094B2
公开(公告)日：2018-12-25
申请号：US15640127
申请日：2017-06-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Kuo-Chi Tu , Jen-Sheng Yang , Sheng-Hung Shih , Tong-Chern Ong , Wen-Ting Chu
IPC: H01L29/78 , G11C11/22 , H01L27/1159 , H01L27/11592 , H01L29/51 , H01L29/66
Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.
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公开(公告)号：US09941470B2
公开(公告)日：2018-04-10
申请号：US15403399
申请日：2017-01-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jen-Sheng Yang , Chih-Yang Chang , Chin-Chieh Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Yu-Wen Liao , Manish Kumar Singh
CPC classification number: H01L45/1253 , H01L27/2436 , H01L45/08 , H01L45/122 , H01L45/146 , H01L45/1666 , H01L45/1691
Abstract: The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.
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公开(公告)号：US20170207387A1
公开(公告)日：2017-07-20
申请号：US15403399
申请日：2017-01-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jen-Sheng Yang , Chih-Yang Chang , Chin-Chieh Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Yu-Wen Liao , Manish Kumar Singh
IPC: H01L45/00
CPC classification number: H01L45/1253 , H01L27/2436 , H01L45/08 , H01L45/122 , H01L45/146 , H01L45/1666 , H01L45/1691
Abstract: The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.
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