公开(公告)号：US20220059679A1

公开(公告)日：2022-02-24

申请号：US16996665

申请日：2020-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao LIU ,  Huicheng CHANG ,  Chien-Tai CHAN ,  Liang-Yin CHEN ,  Yee-Chia YEO ,  Szu-Ying CHEN

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.

公开(公告)号：US20210305092A1

公开(公告)日：2021-09-30

申请号：US16997616

申请日：2020-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Cheng CHEN ,  Huicheng CHANG ,  Fu-Ming HUANG ,  Kei-Wei CHEN ,  Liang-Yin CHEN ,  Tang-Kuei CHANG ,  Yee-Chia YEO ,  Wei-Wei LIANG ,  Ji CUI

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/532 ,  H01L23/522 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L23/535

Abstract: The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

公开(公告)号：US20190157456A1

公开(公告)日：2019-05-23

申请号：US16038866

申请日：2018-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng CHEN ,  Su-Hao LIU ,  Kuo-Ju CHEN ,  Liang-Yin CHEN

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L27/088

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes forming a modified region in the epitaxial structure. The modified region has lower crystallinity than an inner portion of the epitaxial structure and extends along an entirety of an exposed surface of the epitaxial structure. The method also includes forming a semiconductor-metal compound region on the epitaxial structure. All or some of the modified region is transformed into the semiconductor-metal compound region.

公开(公告)号：US20190131399A1

公开(公告)日：2019-05-02

申请号：US15797703

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao LIU ,  Huicheng CHANG ,  Chia-Cheng CHEN ,  Liang-Yin CHEN ,  Kuo-Ju CHEN ,  Chun-Hung WU ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/265 ,  H01L21/285 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US20170125536A1

公开(公告)日：2017-05-04

申请号：US14925657

申请日：2015-10-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Heng CHEN ,  Wayne LIU ,  Liang-Yin CHEN ,  Xiong-Fei YU ,  Hui-Cheng CHANG

IPC: H01L29/49 ,  H01L21/324 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78

Abstract: A method of fabricating the gate structure in a semiconductor device includes forming a gate dielectric layer over a semiconductor substrate. A capping layer is formed over the gate dielectric layer. The capping layer is treated with a first hydrogen plasma to form a first-treated capping layer. A gate electrode is formed over the first-treated capping layer. The method may further includes treating the first-treated capping layer with a nitrogen plasma.