Dual gate biologically sensitive field effect transistor

    公开(公告)号:US10161901B2

    公开(公告)日:2018-12-25

    申请号:US14961588

    申请日:2015-12-07

    Abstract: A biologically sensitive field effect transistor includes a substrate, a first control gate and a second control gate. The substrate has a first side and a second side opposite to the first side, a source region and a drain region. The first control gate is disposed on the first side of the substrate. The second control gate is disposed on the second side of the substrate. The second control gate includes a sensing film disposed on the second side of the substrate. A voltage biasing between the source region and the second control gate is smaller than a threshold voltage of the second control gate.

    Systems and Methods a High Gain Bandwidth Low Power Trans-Impedance Voltage Gain Amplifier (TIVA) Topology
    17.
    发明申请
    Systems and Methods a High Gain Bandwidth Low Power Trans-Impedance Voltage Gain Amplifier (TIVA) Topology 有权
    系统和方法高增益带宽低功率反阻抗电压增益放大器(TIVA)拓扑

    公开(公告)号:US20140097902A1

    公开(公告)日:2014-04-10

    申请号:US13647468

    申请日:2012-10-09

    CPC classification number: H03B5/30 H03F2200/36 H03G3/3036

    Abstract: An amplifier and oscillator system includes a MEMS resonator and a two stage amplifier topology. The MEMS resonator is configured to generate a resonator signal. The two-stage amplifier topology is configured to amplify the resonator signal with a selected trans-impedance gain. Additionally, the two stage amplifier topology yields a feedback resistance that provides the selected trans-impedance gain.

    Abstract translation: 放大器和振荡器系统包括MEMS谐振器和两级放大器拓扑。 MEMS谐振器被配置为产生谐振器信号。 两级放大器拓扑被配置为以选定的跨阻增益放大谐振器信号。 另外,两级放大器拓扑产生提供所选择的跨阻抗增益的反馈电阻。

    Layout of a MOS Array Edge with Density Gradient Smoothing
    18.
    发明申请
    Layout of a MOS Array Edge with Density Gradient Smoothing 有权
    具有密度梯度平滑的MOS阵列边缘的布局

    公开(公告)号:US20130285190A1

    公开(公告)日:2013-10-31

    申请号:US13744532

    申请日:2013-01-18

    CPC classification number: G06F17/5072 H01L27/0207 H01L27/04

    Abstract: A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.

    Abstract translation: 公开了一种多步密度梯度平滑布局样式,其中多个单位单元被布置成具有特征密度的阵列。 阵列的一个或多个边缘由第一边缘子阵列界定,该第一边缘子阵列的特征密度小于阵列的特征密度。 第一边缘子阵列由第二边缘子阵列邻接,第二边缘子阵列的特征密度小于第一边缘子阵列的特征密度,并且接近背景电路的特征密度。

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